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| order this document by mc68HC11EA9ts/d m this document contains information on a new product. specifications and information herein are subject to change without notice. ?motorola inc., 1995, 1997 motorola semiconductor technical data mc68HC11EA9 mc68hc711ea9 technical summary 8-bit microcontrollers 1 introduction the mc68HC11EA9 and mc68hc711ea9 microcontroller units (mcus) are high-performance mem- bers of the m68hc11 family of mcus. the mc68hc(7)11ea9 mcus have a multiplexed external ad- dress and data bus and are characterized by high speed and low power consumption. their fully static design allows operation at frequencies from 3 mhz to dc. the addition of a phase-locked loop (pll) frequency synthesizer to the timer circuitry further enhances low-power operation and allows the use of lower frequency crystals while maintaining a clock speed of up to 3 mhz. this document contains information concerning standard and custom-rom devices. standard devices are those with rom or with eprom replacing rom (mc68hc711ea9). custom-rom devices have a rom array that is programmed at the factory to customer specifications. where information in this doc- ument refers to both the rom and eprom versions, the device is referred to as mc68hc(7)11ea9. 1.1 features ?m68hc11 cpu ?512 bytes ram (data retained during standby, by use of v stby ) ?12 kbytes mask-programmed rom or eprom ?512 bytes electrically erasable programmable rom (eeprom) ?prog mode allows use of standard eprom programmer (27c256 footprint) ?multiplexed address and data buses reduce pin count ?enhanced 16-bit timer with four-stage programmable prescaler ?three input capture (ic) channels ?four output compare (oc) channels ?one additional channel, selectable as fourth ic or fifth oc ?8-bit pulse accumulator ?phase-locked loop (pll) frequency synthesizer for reduced power consumption ?power saving stop and wait modes ?real-time interrupt circuit ?computer operating properly (cop) watchdog timer ?clock monitor circuit ?enhanced asynchronous nonreturn to zero (nrz) serial communications interface (sci) ?eight-channel 8-bit analog-to-digital (a/d) converter ?five input/output (i/o) ports (34 pins) ?four bidirectional i/o ports (26 pins) ?one fixed input-only port (8 pins) ?two alternate, fixed input-only pins (xirq pin/xpin bit and irq pin/ipin bit) ?available in 52-pin plastic leaded chip carrier (plcc), 52-pin windowed ceramic leaded chip carrier (clcc), and 56-pin sdip (0.070?lead spacing) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
section page motorola mc68HC11EA9 2 mc68HC11EA9ts/d 1 introduction 1 1.1 features ...................................................................................................................................... 1 2 device package options and ordering information 5 2.1 available device packages ......................................................................................................... 5 2.2 ordering information ................................................................................................................... 7 3 central processing unit 8 3.1 programming model .................................................................................................................... 8 3.2 cpu registers ............................................................................................................................. 8 3.2.1 accumulators a, b, and d ................................................................................................ 8 3.2.2 index register x (ix) ....................................................................................................... 8 3.2.3 index register y (iy) ....................................................................................................... 9 3.2.4 stack pointer (sp) ............................................................................................................ 9 3.2.5 program counter (pc) ...................................................................................................... 9 3.2.6 condition code register (ccr) ....................................................................................... 9 3.2.7 addressing modes ............................................................................................................ 9 4 operating modes and on-chip memory 10 4.1 single-chip mode ...................................................................................................................... 10 4.2 expanded mode ........................................................................................................................ 10 4.3 test mode ................................................................................................................................. 11 4.4 bootstrap mode ......................................................................................................................... 11 4.5 mode selection .......................................................................................................................... 11 4.6 ram .......................................................................................................................................... 12 4.7 bootstrap rom .......................................................................................................................... 12 4.8 memory map and register block .............................................................................................. 12 4.9 rom/eprom/otprom ........................................................................................................... 15 4.9.1 eprom emulation mode ............................................................................................... 15 4.9.2 programming an individual eprom address ................................................................ 16 4.9.3 programming eprom with downloaded data ............................................................... 17 4.10 eeprom ................................................................................................................................... 18 4.10.1 programming and erasing eeprom ............................................................................. 18 4.10.2 config register ........................................................................................................... 20 4.10.3 eeprom security .......................................................................................................... 21 5 resets and interrupts 22 6 parallel input/output 26 7 timing system 31 7.1 phase-locked loop synthesizer ............................................................................................... 32 7.2 main timer ................................................................................................................................ 34 7.3 real-time interrupt ................................................................................................................... 42 7.4 pulse accumulator .................................................................................................................... 43 8 serial communications interface 47 9 analog-to-digital converter 54 table of contents f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC11EA9 motorola mc68HC11EA9ts/d 3 register index adctl . . . . . . . . . a/d control/status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1030 . . . . . . . . . . . . . . 62 adr1?dr4 . . . . a/d results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1031?1034 . . . . . . . . 63 bprot . . . . . . . . . eeprom block protect . . . . . . . . . . . . . . . . . . . . . . . . . .$1035 . . . . . . . . . . . . . . 21 cforc . . . . . . . . . timer compare force . . . . . . . . . . . . . . . . . . . . . . . . . . .$100b . . . . . . . . . . . . . . 41 config . . . . . . . . security, cop, rom/eprom/eeprom enables . . . . . .$103f . . . . . . . . . . . 23, 28 coprst . . . . . . . . arm/reset cop timer circuitry . . . . . . . . . . . . . . . . . . . .$103a . . . . . . . . . . . . . . 27 ddra . . . . . . . . . . port a data direction . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1001 . . . . . . . . . . . . . . 32 ddrb . . . . . . . . . . port b data direction . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1006 . . . . . . . . . . . . . . 32 ddrc . . . . . . . . . . port c data direction . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1007 . . . . . . . . . . . . . . 33 ddrd . . . . . . . . . . port d data direction . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1009 . . . . . . . . . . . . . . 34 hprio . . . . . . . . . highest priority i-bit interrupt and miscellaneous. . . . . . .$103c . . . . . . . . . . . 12, 27 init . . . . . . . . . . . . ram and i/o mapping register . . . . . . . . . . . . . . . . . . . .$103d . . . . . . . . . . . . . . 14 oc1d . . . . . . . . . . output compare 1 data . . . . . . . . . . . . . . . . . . . . . . . . . .$100d . . . . . . . . . . . . . . 41 oc1m . . . . . . . . . . output compare 1 mask . . . . . . . . . . . . . . . . . . . . . . . . .$100c . . . . . . . . . . . . . . 41 option . . . . . . . . system configuration options . . . . . . . . . . . . . . . . . . . . .$1039 . . . . . . . . 26, 47, 63 pacnt . . . . . . . . . pulse accumulator counter . . . . . . . . . . . . . . . . . . . . . . .$1027 . . . . . . . . . . . . . . 51 pactl . . . . . . . . . pulse accumulator control. . . . . . . . . . . . . . . . . . . . . . . .$1026 . . . . . . . . 46, 49, 50 pprog . . . . . . . . . eprom and eeprom programming control register. .$103b . . . . . . . . . . . 19, 22 pioc . . . . . . . . . . . port i/o control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1002 . . . . . . . . . . . . . . 30 pllcr . . . . . . . . . pll control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1036 . . . . . . . . . . . . . . 37 porta . . . . . . . . . port a data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1000 . . . . . . . . . . . . . . 31 portb . . . . . . . . . port b data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1004 . . . . . . . . . . . . . . 32 portc . . . . . . . . . port c data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1003 . . . . . . . . . . . . . . 32 portcl . . . . . . . . port c latched data. . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1005 . . . . . . . . . . . . . . 33 portd . . . . . . . . . port d data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1008 . . . . . . . . . . . . . . 33 porte . . . . . . . . . port e data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$100a . . . . . . . . . . . . . . . 34 scbdh/l . . . . . . . sci baud rate select high/low . . . . . . . . . . . . . . . . . . .$1028, $1029 . . . . . . . . 56 sccr1 . . . . . . . . . sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .$102a . . . . . . . . . . . . . . 57 sccr2 . . . . . . . . . sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .$102b . . . . . . . . . . . . . . 57 scdrh/l . . . . . . . sci data high, sci data low . . . . . . . . . . . . . . . . . . . . .$102e, $102f . . . . . . . . 59 scsr1 . . . . . . . . . sci status register 1. . . . . . . . . . . . . . . . . . . . . . . . . . . .$102c . . . . . . . . . . . . . . 58 scsr2 . . . . . . . . . sci status register 2. . . . . . . . . . . . . . . . . . . . . . . . . . . .$102d . . . . . . . . . . . . . . 59 synr . . . . . . . . . . frequency synthesizer control . . . . . . . . . . . . . . . . . . . .$1037 . . . . . . . . . . . . . . 38 tcnt . . . . . . . . . . timer counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$100e?100f . . . . . . . . 41 tctl1 . . . . . . . . . . timer control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1020 . . . . . . . . . . . . . . 43 tctl2 . . . . . . . . . . timer control 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1021 . . . . . . . . . . . . . . 43 tflg1 . . . . . . . . . timer interrupt flag 1. . . . . . . . . . . . . . . . . . . . . . . . . . . .$1023 . . . . . . . . . . . . . . 44 tflg2 . . . . . . . . . timer interrupt flag 2. . . . . . . . . . . . . . . . . . . . . . . . . . . .$1025 . . . . . . . . 45, 48, 52 ti4/o5 . . . . . . . . . . timer input capture 4/output compare 5 . . . . . . . . . . . .$101e?101f . . . . . . . . 42 tic1?ic3 . . . . . . timer input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . .$1010?1015 . . . . . . . . 42 tmsk1 . . . . . . . . . timer interrupt mask 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .$1022 . . . . . . . . . . . . . . 43 tmsk2 . . . . . . . . . timer interrupt mask 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .$1024 . . . . . . . . . . . 44, 51 toc1?oc4 . . . . . timer output compare . . . . . . . . . . . . . . . . . . . . . . . . . .$1016?101d . . . . . . . . 42 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68HC11EA9 4 mc68HC11EA9ts/d figure 1 mc68hc(7)11ea9 block diagram control ea9 block pc7/addr7/data7 pc6/addr6/data6 pc5/addr5/data5 pc4/addr4/data4 pc3/addr3/data3 pc2/addr2/data2 pc1/addr1/data1 pc0/addr0/data0 mode control osc clock logic interrupt logic 512 bytes eeprom 512 bytes ram serial communication interface sci m68hc11 cpu control port d port e pe7/an7 txd rxd pd0/rxd stra/as strb/r/w address/data bus expansion address as strobe and handshake parallel i/o strb stra control port c port b pb7/addr15 port a pa7/pai timer system cop pulse accumulator oc2 oc3 oc4 oc5/ic4/oc1 ic1 ic2 ic3 pai periodic interrupt moda/ lir modb/ v stby xtal extal e irq/ v ppee reset pd1/txd r/w pa6/oc2/oc1 pa5/oc3/oc1 pa4/oc4/oc1 pa3/oc5/ic4/oc1 pa2/ic1 pa1/ic2 pa0/ic3 pb6/addr14 pb5/addr13 pb4/addr12 pb3/addr11 pb2/addr10 pb1/addr9 pb0/addr8 pe6/an6 pe5/an5 pe4/an4 pe3/an3 pe2/an2 pe1/an1 pe0/an0 v dd v ss v rh v rl xirq/ v ppe * * v ppe applies only to devices with eprom/otprom. 12 kbytes rom/eprom a/d converter control pll xfc v ddsyn ipin xpin f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC11EA9 motorola mc68HC11EA9ts/d 5 2 device package options and ordering information 2.1 available device packages the mc68hc(7)11ea9 mcus are available in a 52-pin plastic leaded chip carrier (plcc) and a 52-pin ceramic leaded chip carrier (clcc). refer to figure 2 . a plastic 56-pin shrink dip (sdip) package is also available. refer to figure 3 . the eprom-based mc68hc711ea9 is available in a windowed 52-pin ceramic leaded chip carrier (clcc). a one-time-programmable (otp) version of the mc68hc711ea9 is available by ordering the device in a non-windowed package. refer to table 1 . figure 2 mc68hc(7)11ea9 plcc/clcc pin assignments ea9 52-pin plcc pe4/an4 pe0/an0 pb0/addr8 pb1/addr9 pb2/addr10 pb3/addr11 pb4/addr12 pb5/addr13 pb6/addr14 pb7/addr15 pa0/ic3 extal strb/r/w e stra/as moda/lir v dd v ss v rh v rl pe7/an7 pe3/an3 xtal pc0/addr0/data0 pc1/addr1/data1 pc2/addr2/data2 pc3/addr3/data3 pc4/addr4/data4 pc5/addr5/data5 pc6/addr6/data6 pc7/addr7/data7 reset xirq/v ppe pd1/txd modb/v stby v ddsyn xfc v ss v dd pa7/pai/oc1 pa6/oc2/oc1 pa5/oc3/oc1 pa4/oc4/oc1 pa3/oc5/ic4/oc1 mc68hc(7)11ea9 8 9 10 11 12 13 14 15 16 17 44 43 42 41 40 39 38 37 36 35 34 21 22 23 24 25 26 27 28 29 30 31 7 6 5 4 3 1 2 52 51 50 49 irq/v ppee 18 pd0/rxd 19 pa2/ic1 32 pa1/ic2 33 pe6/an6 48 pe2/an2 47 pe1/an1 45 pe5/an5 46 20 * * v ppe applies only to devices with eprom/otprom. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68HC11EA9 6 mc68HC11EA9ts/d figure 3 mc68hc(7)11ea9 56-pin sdip pin assignments ea9 56-pin dip * v ppe applies only to mc68hc711ea9. pc0/addr0/data0 pc1/addr1/data1 pc2/addr2/data2 pc3/addr3/data3 pc4/addr4/data4 pc5/addr5/data5 pc6/addr6/data6 pc7/addr7/data7 reset xirq/v ppe mc68hc(7)11ea9 (0.070" spacing) 9 10 11 12 13 14 15 16 17 18 irq/v ppee 19 20 21 * 22 pd1/txd 23 modb/v stby 24 v ddsyn 25 xfc 26 v ss 27 v dd 28 xtal 8 nc 7 strb/r/w 6 e 5 stra/as 4 3 2 v dd 1 pe0/an0 pb0/addr8 pb1/addr9 pb2/addr10 pb3/addr11 pb4/addr12 pb5/addr13 pb6/addr14 pb7/addr15 nc pa1/ic2 46 45 44 43 42 41 40 39 38 37 36 pe4/an4 47 pe1/an1 48 pa2/ic1 35 pa3/oc5/ic4/oc1 34 pa4/oc4/oc1 33 pa5/oc3/oc1 32 pa6/oc2/oc1 31 pa7/pai/oc1 30 29 pe5/an5 49 pe2/an2 50 pe6/an6 51 pe3/an3 52 pe7/an7 53 v rl 54 v rh 55 v ss 56 pd0/rxd v ss moda/lir extal nc pa0/ic3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC11EA9 motorola mc68HC11EA9ts/d 7 2.2 ordering information the mc68hc(7)11ea9 mcus are available in a combination of packages, speeds, and temperature ranges. refer to table 1 . table 1 device ordering information description package temperature frequency mc order number buffalo rom 52-pin plcc ?40 to + 85 c 2 mhz mc68HC11EA9bcfn2 12 kbytes rom, 2 mhz mc68HC11EA9cfn2 512 bytes ram 3 mhz mc68HC11EA9cfn3 ?40 to + 105 c 2 mhz mc68HC11EA9vfn2 3 mhz mc68HC11EA9vfn3 ?40 to + 125 c 2 mhz mc68HC11EA9mfn2 3 mhz mc68HC11EA9mfn3 56-pin sdip ?40 to + 85 c 2 mhz mc68HC11EA9cp2 (.070?spacing) 3 mhz mc68HC11EA9cp3 ?40 to + 105 c 2 mhz mc68HC11EA9vp2 3 mhz mc68HC11EA9vp3 ?40 to + 125 c 2 mhz mc68HC11EA9mp2 3 mhz mc68HC11EA9mp3 12 kbytes otprom, 52-pin plcc ?40 to + 85 c 2 mhz mc68hc711ea9cfn2 512 bytes ram 3 mhz mc68hc711ea9cfn3 ?40 to + 105 c 2 mhz mc68hc711ea9vfn2 3 mhz mc68hc711ea9vfn3 ?40 to + 125 c 2 mhz mc68hc711ea9mfn2 3 mhz mc68hc711ea9mfn3 56-pin sdip ?40 to + 85 c 2 mhz mc68hc711ea9cp2 (.070?spacing) 3 mhz mc68hc711ea9cp3 ?40 to + 105 c 2 mhz mc68hc711ea9vp2 3 mhz mc68hc711ea9vp3 ?40 to + 125 c 2 mhz mc68hc711ea9mp2 3 mhz mc68hc711ea9mp3 12 kbytes eprom, 52-pin clcc ?40 to + 85 c 2 mhz mc68hc711ea9cfs2 512 bytes ram (windowed) 3 mhz mc68hc711ea9cfs3 ?40 to + 105 c 2 mhz mc68hc711ea9vfs2 3 mhz mc68hc711ea9vfs3 ?40 to + 125 c 2 mhz mc68hc711ea9mfs2 3 mhz mc68hc711ea9mfs3 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68HC11EA9 8 mc68HC11EA9ts/d 3 central processing unit a full description of the cpu and instruction set of m68hc11 mcus is beyond the scope of this sum- mary. the programming model for the m68hc11 cpu and a brief description of the cpu registers is provided here. for more detailed information refer to the m68hc11 reference manual (m68hc11rm/ ad) or the programming reference guide or technical data book for the appropriate device. 3.1 programming model figure 4 shows a graphic representation of the internal registers of the m68hc11 cpu. figure 4 m68hc11 programming model 3.2 cpu registers m68hc11 cpu registers are an integral part of the cpu and are not addressed as if they were memory locations. the seven registers, discussed briefly in the following paragraphs, are shown in figure 4 . for a complete description of the cpu registers, addressing modes, and instruction set refer to the m68hc11 reference manual (m68hc11rm/ad). 3.2.1 accumulators a, b, and d accumulators a and b are general-purpose 8-bit registers that hold operands and results of arithmetic calculations or data manipulations. for some instructions, these two accumulators are treated as a sin- gle double-byte (16-bit) accumulator called accumulator d. most instructions can use accumulators a or b interchangeably, however some exceptions apply. 3.2.2 index register x (ix) the ix register provides a 16-bit indexing value that can be added to the 8-bit offset provided in an in- struction to create an effective address. the ix register can also be used as a counter or as a temporary storage register. hc11 prog model 7 15 15 15 15 15 07 0 0 0 0 0 0 accumulator a accumulator b double accumulator d index register x index register y stack pointer program counter condition code register sxhi nzvc ccr a:b d ix iy sp pc carry overflow zero negative i interrupt mask half carry (from bit 3) x interrupt mask stop disable f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC11EA9 motorola mc68HC11EA9ts/d 9 3.2.3 index register y (iy) the 16-bit iy register performs an indexed mode function similar to that of the ix register. however, most instructions using the iy register require an extra byte of machine code and an extra cycle of ex- ecution time because of the way the opcode map is implemented. 3.2.4 stack pointer (sp) the m68hc11 cpu has an automatic program stack. this stack can be located anywhere in the ad- dress space and can be any size up to the amount of memory available in the system. normally the sp is initialized by one of the first instructions in an application program. the stack is configured as a data structure that grows downward from high memory to low memory. each time a new byte is pushed onto the stack, the sp is decremented. each time a byte is pulled from the stack, the sp is incremented. at any given time, the sp holds the 16-bit address of the next free location in the stack. 3.2.5 program counter (pc) the program counter, a 16-bit register, contains the address of the next instruction to be executed. after reset, the program counter is initialized from one of six possible vectors, depending on operating mode and the cause of reset. 3.2.6 condition code register (ccr) this 8-bit register contains five condition code indicators (c, v, z, n, and h), two interrupt masking bits, (irq and xirq ) and a stop disable bit (s). in the m68hc11 cpu, condition codes are automatically updated by most instructions. for example, load accumulator a (ldaa) and store accumulator a (staa) instructions automatically set or clear the n, z, and v condition code flags. 3.2.7 addressing modes six addressing modes can be used to access memory: immediate, direct, extended, indexed, inherent, and relative. these modes are not detailed in this manual. for a complete description of the cpu reg- isters, addressing modes, and instruction set refer to the m68hc11 reference manual (m68hc11rm/ ad). f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68HC11EA9 10 mc68HC11EA9ts/d 4 operating modes and on-chip memory 4.1 single-chip mode in single-chip mode, ports b and c are available for general-purpose parallel i/o. strobe pins a (stra) and b (strb) can be used to control handshaking of parallel i/o on ports b and c. in this mode, all software needed to control the mcu is contained in internal resources. rom/eprom (if present) will always be enabled out of reset, ensuring that the reset and interrupt vectors will be available at locations $ffc0?ffff. 4.2 expanded mode in expanded operating mode, the mcu can access the full 64-kbyte address space. the space includes the same on-chip memory addresses used for single-chip mode as well as addresses for external pe- ripherals and memory devices. the expansion bus is made up of ports b and c, and control signals as and r/w . r/w (read/write) and as (address strobe) allow the low-order address and the 8-bit data bus to be multiplexed on the same pins. during the first half of each bus cycle address information is present. during the second half of each bus cycle the pins become the bidirectional data bus. as is an active-high latch enable signal for an external address latch. address information is allowed through the transparent latch while as is high and is latched when as drives low. figure 5 shows an example of address and data demultiplexing. figure 5 address/data demultiplexing addr/data demux r/w e we mc54/74hc373 as mcu pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 addr15 addr14 addr13 addr12 addr11 addr10 addr9 addr8 addr7 addr6 addr5 addr4 addr3 addr2 addr1 addr0 data1 data2 data3 data4 data5 data6 data7 data8 le data7 data6 data5 data4 data3 data2 data1 data0 q1 q2 q3 q4 q5 q6 q7 q8 q0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC11EA9 motorola mc68HC11EA9ts/d 11 4.3 test mode test mode, a variation of the expanded mode, is primarily used during motorola's internal production testing; however, it is accessible for programming the config register, programming calibration data into eeprom, and supporting emulation and debugging during development. refer to figure 6 . 4.4 bootstrap mode bootstrap mode is a special variation of the single-chip mode. bootstrap mode allows special-purpose programs to be entered into internal ram. when boot mode is selected at reset, a small bootstrap rom becomes present in the memory map. reset and interrupt vectors are located in this rom at $bfc0 $bfff. the bootstrap rom contains a small program which initializes the sci and allows the user to download a program into on-chip ram. the size of the downloaded program can be as large as the size of the on-chip ram. after a four-character delay, or after receiving the character for the highest address in ram, control passes to the loaded program at $0000. refer to figure 6 . 4.5 mode selection the four mode variations are selected by the logic levels present on the moda and modb pins during reset. the moda and modb logic levels determine the logic state of smod and the mda control bits in the highest priority i-bit interrupt and miscellaneous (hprio) register. see table 2 for further infor- mation. after reset is released, the mode select pins no longer influence the mcu operating mode. in single- chip operating mode, the moda pin is connected to a logic level zero. in expanded mode, moda is normally connected to v dd through a pull-up resistor of 4.7 k w . the moda pin also functions as the load instruction register (lir ) pin when the mcu is not in reset. the lir signal is useful during program debugging. the open-drain active low lir output pin drives low during the first e cycle of each instruc- tion. the modb pin also functions as standby power input (v stby ), which allows ram contents to be maintained in absence of v dd . *the reset values of rboot, smod, and mda depend on the mode selected at power up. rboot ?read bootstrap rom/eprom valid only when smod is set (bootstrap or special test mode). can only be written in special modes. 0 = bootstrap rom disabled and not in map 1 = bootstrap rom enabled and in map at $bf00?bfff smod and mda ?special mode select and mode select a these two bits can be read at any time. they can be written anytime in special modes. mda can only be written once in normal modes. smod cannot be set once it has been cleared. hprio highest priority i-bit interrupt and miscellaneous $103c bit 7 654321 bit 0 rboot* smod* mda* irvne psel3 psel2 psel1 psel0 reset: 00000000 table 2 operating mode selection inputs mode latched at reset moda modb mda smod 0 1 single chip 0 0 1 1 expanded 1 0 0 0 bootstrap 0 1 1 0 special test 1 1 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68HC11EA9 12 mc68HC11EA9ts/d irv(ne) ?internal read visibility(not e) irvne can be written once in any mode. in expanded modes, irvne determines whether irv is on or off. in special test mode, irvne is reset to one. in all other modes, irvne is reset to zero. 0 = no internal read visibility on external bus 1 = data from internal reads is driven out the external data bus. in single-chip modes this bit determines whether the e clock drives out from the chip. 0 = e is driven out from the chip. 1 = e pin is driven low. refer to the following table. psel[3:0] ?priority select bits [3:0] refer to 5 resets and interrupts 4.6 ram in all modes ram is enabled and present at locations $0000?01ff. the ram can be mapped to any 1-kbyte boundary by writing an appropriate value to the init register. the init register must be written during the first 64 cycles after reset in expanded and single-chip modes. if ram and the register block are placed at the same 1-kbyte boundary, the first 64 bytes of ram are inaccessible. this is due to an on-chip hardware priority scheme which eliminates conflicts which could arise from multiple resources sharing address locations. figure 6 shows the location of the ram array. 4.7 bootstrap rom when operating in normal modes (smod = 0), the bootstrap rom is disabled and removed from the memory map. in bootstrap and special test modes, bootstrap rom is present at $bf00?bfff. boot- strap rom cannot be remapped to other locations. figure 6 shows the location of the bootstrap rom array. the bootstrap rom contains a small program that allows program code to be downloaded into on-chip ram. when the mc68hc(7)11ea9 enters bootstrap mode, bootloader firmware residing in bootstrap rom begins the downloading procedure by initializing the sci system and transmitting a break out the sci txd pin. the sci then waits for the first character to be received. after the first character is received on the rxd pin of the sci, bootloader firmware begins counting the number of bytes received. when an idle time of four characters or the character for address $01ff is received, the bootloader program terminates the download and control is passed to the loaded program at $0000. for a detailed descrip- tion of the m68hc11 bootstrap mode, refer to application note m68hc11 bootstrap mode (an1060/d). 4.8 memory map and register block the operating mode determines memory mapping and whether external addresses can be accessed. memory locations for on-chip resources are the same for both expanded and single-chip modes. con- trol bits in the config register allow rom/eprom and eeprom to be disabled from the memory map. the ram is mapped to $0000 after reset. it can be placed at any 4 kbyte boundary ($x000) by writing an appropriate value to the init register. the 64-byte register block is mapped to $1000 after reset and can also be placed at any 4 kbyte boundary ($x000) by writing an appropriate value to the init register. if ram and registers are mapped to the same boundary, the first 64 bytes of ram will be inaccessible. table 4 shows the arrangement of control registers and bits within the register block. table 3 irvne control vs. operating mode operating mode irvne bit out of reset e clock out of reset irv function out of reset irvne bit affects only single chip 0 on off e expanded 0 on off irv bootstrap 0 on off e special test 1 on on irv f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC11EA9 motorola mc68HC11EA9ts/d 13 figure 6 mc68hc(7)11ea9 memory map ram[3:0] ?ram map position these four bits, which specify the upper hexadecimal digit of the ram address, control position of ram in the memory map. ram can be positioned at the beginning of any 4 kbyte page in the memory map. it is initialized to address $0000 out of reset. reg[3:0] ?64-byte register block position these four bits specify the upper hexadecimal digit of the address for the 64-byte block of internal reg- isters. the register block, positioned at the beginning of any 4 kbyte page in the memory map, is initial- ized to address $1000 out of reset. init ram and i/o mapping register $103d bit 7 654321 bit 0 ram3 ram2 ram1 ram0 reg3 reg2 reg1 reg0 reset: 00000001 ea9 mem map aa aa ffc0 ffff normal modes interrupt vectors 64-byte register block 512 bytes ram single chip bootstrap special test ext aa aa aa aa aa aa aa aa $0000 $1000 $b600 $d000 $ffff 0000 1000 103f bf00 expanded d000 ffff bfff bfc0 bfff special modes interrupt vectors b600 b7ff 512 bytes eeprom 12 kbytes rom/eprom boot rom ext ext ext ext ext 01ff aa aa aa aa f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68HC11EA9 14 mc68HC11EA9ts/d table 4 mc68hc(7)11ea9 registers (sheet 1 of 2) bit 7 654321 bit 0 $1000 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 porta $1001 dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 ddra $1002 staf stai cwom hnds oin pls ega invb pioc $1003 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 portc $1004 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 portb $1005 pcl7 pcl6 pcl5 pcl4 pcl3 pcl2 pcl1 pcl0 portcl $1006 ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb $1007 ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 ddrc $1008 xpin ipin 0000pd1pd0 portd $1009 disx disi 0000 ddd1 ddd0 ddrd $100a pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 porte $100b foc1 foc2 foc3 foc4 foc5 0 0 0 cforc $100c oc1m7 oc1m6 oc1m5 oc1m4 oc1m3 0 0 0 oc1m $100d oc1d7 oc1d6 oc1d5 oc1d4 oc1d3 0 0 0 oc1d $100e bit 15 14 13 12 11 10 9 bit 8 tcnt (hi) $100f bit 7 654321 bit 0 tcnt (lo) $1010 bit 15 14 13 12 11 10 9 bit 8 tic1 (hi) $1011 bit 7 654321 bit 0 tic1 (lo) $1012 bit 15 14 13 12 11 10 9 bit 8 tic2 (hi) $1013 bit 7 654321 bit 0 tic2 (lo) $1014 bit 15 14 13 12 11 10 9 bit 8 tic3 (hi) $1015 bit 7 654321 bit 0 tic3 (lo) $1016 bit 15 14 13 12 11 10 9 bit 8 toc1 (hi) $1017 bit 7 654321 bit 0 toc1 (lo) $1018 bit 15 14 13 12 11 10 9 bit 8 toc2 (hi) $1019 bit 7 654321 bit 0 toc2 (lo) $101a bit 15 14 13 12 11 10 9 bit 8 toc3 (hi) $101b bit 7 654321 bit 0 toc3 (lo) $101c bit 15 14 13 12 11 10 9 bit 8 toc4 (hi) $101d bit 7 654321 bit 0 toc4 (lo) $101e bit 15 14 13 12 11 10 9 bit 8 ti4/o5 (hi) $101f bit 7 654321 bit 0 ti4/o5 (lo) $1020 om2 ol2 om3 ol3 om4 ol4 om5 ol5 tctl1 $1021 edg4b edg4a edg1b edg1a edg2b edg2a edg3b edg3a tctl2 $1022 oc1i oc2i oc3i oc4i i4/o5i ic1i ic2i ic3i tmsk1 $1023 oc1f oc2f oc3f oc4f i4/o5f ic1f ic2f ic3f tflg1 $1024 toi rtii paovi paii 0 0 pr1 pr0 tmsk2 $1025 tof rtif paovf paif 0000 tflg2 $1026 0 paen pamod pedge 0 i4/o5 rtr1 rtr0 pactl $1027 bit 7 654321 bit 0 pacnt $1028 btst bspl brst sbr12 sbr11 sbr10 sbr9 sbr8 scbdh $1029 sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 scbdl $102a loops woms 0 m wake ilt pe pt sccr1 $102b tie tcie rie ilie te re rwu sbk sccr2 $102c tdre tc rdrf idle or nf fe pf scsr1 $102d 0000000raf scsr2 $102e r8 t8 000000 scdrh f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC11EA9 motorola mc68HC11EA9ts/d 15 4.9 rom/eprom/otprom the mc68HC11EA9 contains 12 kbytes of mask-programmed rom. the rom array is programmed at the factory to customer specifications and cannot be altered. the rom array can be disabled by clearing the romon bit in the config register. the mc68hc711ea9 mcu contains 12 kbytes of on-chip eprom/otprom. when the mc68hc711ea9 is packaged in a windowed clcc, the 12 kbytes of eprom may be erased by ex- posing the device to ultraviolet light. an mc68hc711ea9 mcu packaged in a non-windowed case con- tains 12 kbytes of one-time-programmable rom (otprom). using the on-chip eprom/otprom programming feature requires an external 12.25-volt power sup- ply (v ppe ). normal programming is accomplished using the eprom/otprom programming register (pprog). pprog is the combined eprom/otprom and eeprom programming register (mc68hc711ea9 only). for the mc68HC11EA9, pprog is used for programming eeprom only. there are three possible methods of programming and verifying eprom. 4.9.1 eprom emulation mode the eprom emulation (prog) mode allows the on-chip eprom/otprom to be programmed as a standard eprom by adapting the mcu footprint to that of the 27256-type eprom, as shown in figure 7 . grounding the reset , moda, and modb pins places the mcu in prog mode. an appropriate eprom programmer can then be used to enter data into the on-chip eprom. figure 7 shows the mcu pin functions while the device is in prog mode. if the mcu is operating with programming voltage present on the xirq /v ppe pin, the irq pin (ce pin in prog mode) must be pulled high before the address and data are changed to program the next lo- cation. note prog mode is disabled in devices having the security feature. $102f r7/t7 r6/t6 r5/t5 r4/t4 r3/t3 r2/t2 r1/t1 r0/t0 scdrl $1030 ccf 0 scan mult cd cc cb ca adctl $1031 bit 7 654321 bit 0 adr1 $1032 bit 7 654321 bit 0 adr2 $1033 bit 7 654321 bit 0 adr3 $1034 bit 7 654321 bit 0 adr4 $1035 0 0 0 ptcon bprt3 bprt2 bprt1 bprt0 bprot $1036 pllon bcs auto bwc vcot mcs lck wen pllcr $1037 synx1 synx0 syny5 syny4 syny3 syny2 syny1 syny0 synr $1038 reserved $1039 adpu csel irqe dly cme 0 cr1 cr0 option $103a bit 7 654321 bit 0 coprst $103b odd even elat 1 byte row erase eelat pgm pprog $103c rboot smod mda irvne psel3 psel2 psel1 psel0 hprio $103d ram3 ram2 ram1 ram0 reg3 reg2 reg1 reg0 init $103e test1 2 $103f 0000 nosec nocop romon eeon config notes: 1. mc68hc711ea9 only. 2. factory test only. table 4 mc68hc(7)11ea9 registers (sheet 2 of 2) bit 7 654321 bit 0 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68HC11EA9 16 mc68HC11EA9ts/d figure 7 mc68hc711ea9 prog mode connections 4.9.2 programming an individual eprom address in the second method, the mcu programs its own eprom by controlling the pprog register. use the following procedure to program the eprom through the mcu with the romon bit set in the config register. the 12 volt nominal programming voltage must be present on the xirq /v ppe pin. any operat- ing mode can be used. 1. write to pprog to set the elat bit. 2. write the data to the desired address. 3. write to pprog to set both the elat and pgm bits. 4. delay for 10 ms or more, as appropriate. 7ea9 prog conn a4 a5 a6 a1 a2 a3 a7 a12 a8 a9 a10 a11 a0 nc extal pa4/oc4/oc1 pa5/oc3/oc1 pc4/addr4/data4 pc5/addr5/data5 pc6/addr6/data6 pc1/addr1/data1 pc2/addr2/data2 pc3/addr3/data3 pc7/addr7/data7 pb4/addr12 pb0/addr8 pb1/addr9 pb2/addr10 pb3/addr11 pc0/addr0/data0 strb/r/w stra/as pa5/oc3/oc1 pa4/oc4/oc1 pa3/oc5/ic4/oc1 pa2/ic1 pd1/txd pd0/rxd o7 o6 o5 o1 o2 o4 o3 o0 a4 a5 a6 a1 a2 a3 a7 a12 a8 a9 a10 a11 a0 a14 gnd note 1 o7 o6 o5 o1 o2 o4 o3 o0 internal 12-kbyte eprom eprom pin functions mcu pin functions eprom mode pin connections mc68hc711ea9 notes: 1. unused inputs ?grounding is recommended. 2. unused outputs ?these pins should be left unterminated. 3. these pins must be grounded for prog mode operation. v ss v dd irq xirq pb7/addr15 gnd v cc ce v pp oe gnd v ce v oe pp cc e xtal pa1/ic2 pa0/ic3 pb6/addr14 gnd gnd gnd gnd note 3 pb5/addr13 a13 reset modb/v stby moda/lir gnd gnd nc nc note 2 a13 nc nc gnd gnd pe0/an0 pe6/an6 gnd pe1/an1 gnd pe2/an2 gnd pe3/an3 gnd pe4/an4 gnd pe5/an5 gnd pe7/an7 gnd rh rl gnd v v gnd v ddsyn gnd xfc pa7/pai/oc1 gnd pa6/oc2/oc1 gnd f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC11EA9 motorola mc68HC11EA9ts/d 17 5. clear the pgm bit to turn off the v ppe voltage. 6. clear all bits in the pprog register to reconfigure the eprom address and data buses for nor- mal operation. note prog mode is initiated when reset , moda , and modb pins are pulled low (the pin state required to enter bootstrap mode). this means that if these three pins are pulled low and v ppe is present on the xirq pin, the eprom will be programmed. to prevent this, place a pull-up resistor on the irq pin (ce pin in prog mode). when the device goes into reset, the pgm bit is forced to the voltage disable state (epgm = 0) before the address/data latches are enabled to the external input lines. only after this occurs is voltage control returned to the irq pin. 4.9.3 programming eprom with downloaded data when using this method, the eprom is programmed by software while in the special test or bootstrap modes. user-developed software can be uploaded through the sci, or a rom resident eprom pro- gramming utility can be used. to use the resident utility, bootload a three-byte program consisting of a single jump instruction to $bf00. $bf00 is the starting address of a resident eprom programming util- ity. the utility program sets the x and y index registers to default values, then receives programming data from an external host and puts it in eprom. the value in ix determines programming delay time. the value in iy is a pointer to the first address in eprom to be programmed (default = $d000). when the utility program is ready to receive programming data, it sends the host the $ff character. then it waits. when the host sees the $ff character, the eprom programming data is sent, starting with the first location in the eprom array. after the last byte to be programmed is sent and the corre- sponding verification data is returned, the programming operation is terminated by resetting the mcu. * mc68hc711ea9 only. odd ?program odd rows in half of eeprom (test) refer to 4.10 eeprom . even ?program even rows in half of eeprom (test) refer to 4.10 eeprom . elat ?eprom/otprom latch control when elat = 1, writes to eprom cause address and data to be latched and the eprom/otprom cannot be read. elat can be read any time. elat can be written any time except when epgm = 1; then the write to elat is disabled. for mc68hc711ea9, epgm enables the high voltage necessary for both eprom/otprom and eeprom programming. for mc68hc711ea9 elat and eelat are mutually exclusive and cannot both equal one. 0 = eprom address and data bus configured for normal reads 1 = eprom address and data bus configured for programming byte ?byte/other eeprom erase mode refer to 4.10 eeprom . row ?row/all eeprom erase mode refer to 4.10 eeprom . pprog ? eprom and eeprom programming control register $103b bit 7 654321 bit 0 odd even elat* byte row erase eelat pgm reset: 00000001 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68HC11EA9 18 mc68HC11EA9ts/d erase ?erase/normal control for eeprom refer to 4.10 eeprom . eelat ?eeprom latch control 0 = eeprom address and data bus configured for normal reads 1 = eeprom address and data bus configured for programming or erasing pgm ?eprom/otprom/eeprom programming voltage enable 0 = programming voltage to eprom/otprom/eeprom array disconnected 1 = programming voltage to eprom/otprom/eeprom array connected pgm can be read any time and can only be written when elat = 1 (for eprom/otprom program- ming) or when eelat = 1 (for eeprom programming). 4.10 eeprom mc68hc(7)11ea9 mcus contain 512 bytes of eeprom. the 512-byte eeprom is initially located at $b600 after reset, assuming eeprom is enabled in the memory map by the eeon bit in the config register. eeprom can be placed at any 4 kbyte boundary ($x600) by writing appropriate values to the init register. note that eeprom can be mapped such that it contains the vector space. see figure 6 . 4.10.1 programming and erasing eeprom programming and erasing the eeprom is controlled by the pprog register, and is dependent upon the block protect (bprot) register value. the erased state of an eeprom bit is one. during a read operation, bit lines are precharged to one. the floating gate devices of programmed bits conduct and pull the bit lines to zero. unprogrammed bits remain at the precharged level and are read as ones. pro- gramming a bit to one causes no change. programming a bit to zero changes the bit so that subsequent reads return zero. when appropriate bits in the bprot register are cleared, the pprog register controls programming and erasing of the eeprom. the pprog register can be read or written at any time, but logic enforces defined programming and erasing sequences to prevent unintentional changes to data in eeprom. when the eelat bit in the pprog register is cleared, the eeprom can be read as if it were a rom. the on-chip charge pump that generates the eeprom programming voltage from v dd uses mos ca- pacitors, which are relatively small in value. the efficiency of this charge pump and its drive capability are affected by the level of v dd and the frequency of the driving clock. the clock source driving the charge pump is software selectable. when the clock select (csel) bit in the option register is zero, the e clock is used; when csel is one, an on-chip resistor-capacitor (rc) oscillator is used. the rc oscillator should be used when e < 1 mhz. this rc oscillator will drive the a/d circuitry as well as the eeprom charge pump when csel = 1. the eeprom programming voltage connection to the eeprom array is not enabled until there has been a write to pprog with eelat set and pgm cleared. this must be followed by a write to a valid eeprom location or to the config address, and then a write to pprog with both eelat and pgm set. any attempt to set both eelat and pgm during the same write operation results in neither bit being set. the erased state of an eeprom byte is $ff (all ones). to erase the eeprom, ensure that the proper bits of the bprot register are cleared, then complete the following steps using the pprog register: 1. set the erase, eelat, and appropriate byte and row bits in pprog register. 2. write to the appropriate eeprom address with any data. row erase only requires a write to any location in the row. bulk erase is done by writing to any location in the array. 3. set the erase, eelat, eepgm, and appropriate byte and row bits in pprog register. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC11EA9 motorola mc68HC11EA9ts/d 19 4. delay for 10 ms or more, as appropriate. 5. clear the eepgm bit in pprog to turn off the programming voltage. 6. clear the pprog register to reconfigure the eeprom address and data buses for normal op- eration. to program the eeprom, ensure the proper bits of the bprot register are cleared and use the prog register to complete the following steps: 1. set the eelat bit in pprog register. 2. write data to the desired address. 3. set eepgm bit in pprog. 4. delay for 10 ms or more, as appropriate. 5. clear the eepgm bit in pprog to turn off the programming voltage. 6. clear the pprog register to reconfigure the eeprom address and data buses for normal op- eration. caution since it is possible to perform other operations while the eeprom programming/ erase operation is in progress, it is common to start the operation then return to the main program until the 10 ms is completed. when the eelat bit is set at the be- ginning of a program/erase operation, the eeprom is electronically removed from the memory map; thus, it is not accessible during the program/erase cycle. care must be taken to ensure that eeprom resources will not be needed by any rou- tines in the code during the 10 ms program/erase time. active bits in bprot reset to ones in all modes and can only be cleared during the first 64 cycles out of reset. bits can be set only once in normal modes. in special modes, bits can be set and cleared re- peatedly. bits [7:5] ?not implemented always read zero ptcon ?protect config register 0 = config register can be programmed or erased normally 1 = config register cannot be programmed or erased bprt[3:0] ?block protect bits for eeprom when set, these bits protect a block of eeprom from being programmed or electronically erased. ul- traviolet light, however can erase the entire eeprom contents regardless of bprt[3:0] (windowed packages only). when cleared, they allow programming and erasure of the associated block. bprot eeprom block protect $1035 bit 7 654321 bit 0 ptcon bprt3 bprt2 bprt1 bprt0 reset: 00011111 table 5 eeprom block protect bit name block protected block size bprt0 $b600?b61f 32 bytes bprt1 $b620?b65f 64 bytes bprt2 $b660?b6df 128 bytes bprt3 $b6e0?b7ff 288 bytes f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68HC11EA9 20 mc68HC11EA9ts/d * mc68hc711ea9 only. odd ?program odd rows in half of eeprom (test) even ?program even rows in half of eeprom (test) elat ?eprom/otprom latch control mc68hc711ea9 only. refer to 4.9.3 programming eprom with downloaded data . byte ?byte/other eeprom erase mode 0 = row or bulk erase mode used 1 = erase only one byte of eeprom row ?row/all eeprom erase mode (only valid when byte = 0) 0 = all 512 bytes of eeprom erased 1 = erase only one 16-byte row of eeprom erase ?erase/normal control for eeprom 0 = normal read or program mode 1 = erase mode eelat ?eeprom latch control 0 = eeprom address and data bus configured for normal reads 1 = eeprom address and data bus configured for programming or erasing pgm ?eprom/otprom/eeprom programming voltage enable 0 = programming voltage to eprom/otprom/eeprom array disconnected 1 = programming voltage to eprom/otprom/eeprom array connected pgm can be read any time and can only be written when elat = 1 (for eprom/otprom program- ming) or when eelat = 1 (for eeprom programming). 4.10.2 config register the config register consists of an eeprom byte and static latches that control the start-up configu- ration of the mcu. the contents of the eeprom byte are transferred into static working latches during reset sequences. the operation of the mcu is controlled directly by these latches and not by config itself. although the byte is not included in the 512-byte eeprom array, programming the config reg- ister requires the same procedure as any byte in the array. in normal modes, changes to config do not affect operation of the mcu until after the next reset sequence. when programming, the config register itself is accessed. when the config register is read, the static latches are accessed. pprog ? eprom and eeprom programming control register $103b bit 7 654321 bit 0 odd even elat* byte row erase eelat pgm reset: 00000001 table 6 byte/row control bits byte row action 0 0 bulk erase (all 512 bytes) 0 1 row erase (16 bytes) 1 0 byte erase 1 1 byte erase f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC11EA9 motorola mc68HC11EA9ts/d 21 u indicates a previously programmed bit. u(l) indicates that the bit resets to the logic level held in the latch prior to reset (unchanged), but the function of cop is controlled by disr bit in test1 register. bits [7:4] ?not implemented always read zero nosec ?security disable nosec is invalid unless the security mask option is specified before the mcu is manufactured. if se- curity mask option is omitted nosec always reads one. the security feature protects the contents of ram and eeprom. 0 = security enabled 1 = security disabled nocop ?cop system disable refer to 5 resets and interrupts . romon ?rom/eprom/otprom enable when this bit is zero, the rom or eprom/otprom is disabled and that memory space becomes ex- ternally addressed. in single-chip mode, romon is forced to one to enable rom/eprom/otprom regardless of the state of the romon bit. 0 = rom/eprom/otprom disabled from the memory map 1 = rom/eprom/otprom present in the memory map eeon ?eeprom enable when this bit is zero, the eeprom is disabled and that memory space becomes externally addressed. 0 = eeprom removed from the memory map 1 = eeprom present in the memory map 4.10.3 eeprom security the optional security feature, available only on rom-based mcus, protects the eeprom and ram contents from unauthorized access. a program, or a key portion of a program, can be protected against unauthorized duplication. to accomplish this, the protection mechanism restricts operation of protected devices to the single-chip modes. this prevents the memory locations from being monitored externally because single-chip modes do not allow visibility of the internal address and data buses. resident pro- grams, however, have unlimited access to the internal eeprom and ram and can read, write, or trans- fer the contents of these memories. config security, cop, rom/eprom, and eeprom enables $103f bit 7 654321 bit 0 nosec nocop romon eeon resets: s. chip: 0000uu1u boot: 0000u u(l) u u exp.: 00001uuu test: 00001 u(l) u u f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68HC11EA9 22 mc68HC11EA9ts/d 5 resets and interrupts all m68hc11 mcus have three reset vectors and 18 interrupt vectors. the reset vectors are as follows: ?reset , or power-on reset ?clock monitor fail ?cop failure the 18 interrupt vectors service 22 interrupt sources (3 non-maskable, 19 maskable). the 3 non- maskable interrupt sources are as follows: ?illegal opcode trap ?software interrupt ?xirq pin (x interrupt) on-chip peripheral systems generate maskable interrupts, which are recognized only if the global inter- rupt mask bit (i) in the condition code register (ccr) is clear. maskable interrupts are prioritized accord- ing to a default arrangement; however, any one source can be elevated to the highest maskable priority position by a software-accessible control register (hprio). the hprio register can be written at any time, provided bit i in the ccr is set. eighteen interrupt sources in the mc68hc(7)11ea9 mcus are subject to masking by the global inter- rupt mask bit (bit i in the ccr). in addition to the global bit i, all of these sources, except the external interrupt (irq ) pin, are controlled by local enable bits in control registers. most interrupt sources in the m68hc11 have separate interrupt vectors; therefore, there is usually no need for software to poll control registers to determine the cause of an interrupt. for some interrupt sources, such as the sci interrupts, the flags are automatically cleared during the normal course of responding to the interrupt requests. for example, the rdrf flag in the sci system is cleared by the automatic clearing mechanism invoked by a read of the sci status register while rdrf is set, followed by a read of the sci data register. the normal response to an rdrf interrupt request would be to read the sci status register to check for receive errors, then to read the received data from the sci data register. these two steps satisfy the automatic clearing mechanism without requiring any special instructions. the computer operating properly (cop) watchdog and the clock monitor are both circuits that force a reset sequence when a malfunctioning clock is encountered. the cop function forces a reset when a timeout occurs. the timeout period is determined by programming cr[1:0] in option register. the clock monitor circuit forces a reset sequence whenever the clock is slow or absent. the cme bit in the option register enables the clock monitor circuit. to use stop mode the clock monitor must be dis- abled before the stop instruction is executed or a reset sequence will occur. refer to the following table for a list of interrupt and reset vector assignments. table 7 interrupt and reset vector assignments vector address interrupt source ccr mask local mask priority (1 = high) ffc0, c1 ?ffd4, d5 reserved ffd6, d7 sci serial system bit i 18 ?sci receive data register full rie ?sci receiver overrun rie ?sci transmit data register empty tie ?sci transmit complete tcie ?sci idle line detect ilie ffd8, d9 reserved f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC11EA9 motorola mc68HC11EA9ts/d 23 adpu ?a/d converter power up refer to 9 analog-to-digital converter csel ?clock select refer to 4.10 eeprom . irqe ?irq select edge-sensitive only 0 = irq input is active-low 1 = irq input recognizes falling edges only dly ?enable oscillator start-up delay 0 = no stabilization delay on exit from stop mode. 1 = a delay of approximately 4000 e-clock cycles is imposed as the mcu exits stop mode. cme ?clock monitor enable 0 = clock monitor disabled; slow clock can be used. 1 = slow or stopped clocks cause cop failure reset. bit 2 ?not implemented always reads zero cr[1:0] ?cop timer rate select refer to the following table of cop timer rates. ffda, db pulse accumulator input edge bit i paii 17 ffdc, dd pulse accumulator overflow bit i paovi 16 ffde, df timer overflow bit i toi 15 ffe0, e1 timer input capture 4/output compare 5 bit i i4/o5i 14 ffe2, e3 timer output compare 4 bit i oc4i 13 ffe4, e5 timer output compare 3 bit i oc3i 12 ffe6, e7 timer output compare 2 bit i oc2i 11 ffe8, e9 timer output compare 1 bit i oc1i 10 ffea, eb timer input capture 3 bit i ic3i 9 ffec, ed timer input capture 2 bit i ic2i 8 ffee, ef timer input capture 1 bit i ic1i 7 fff0, f1 real-time interrupt bit i rtii 6 fff2, f3 irq (external pin) bit i none 5 fff4, f5 xirq pin bit x none 4 fff6, f7 software interrupt none none * fff8, f9 illegal opcode trap none none * fffa, fb cop failure none nocop 3 fffc, fd clock monitor fail none cme 2 fffe, ff reset none none 1 * same level as an instruction option system configuration options $1039 bit 7 654321 bit 0 adpu csel irqe* dly* cme cr1* cr0* reset: 00010000 * can be written only once in first 64 cycles after reset in normal modes, or at any time in special modes. table 7 interrupt and reset vector assignments f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68HC11EA9 24 mc68HC11EA9ts/d write $55 to coprst to arm cop watchdog circuit. write $aa to coprst to reset cop watchdog circuit. *rboot, smod, and mda reset depend on power-up initialization mode and can only be written in special mode. rboot ?read bootstrap rom refer to 4.4 bootstrap mode smod ?special mode select refer to 4.5 mode selection mda ?mode select a refer to 4.5 mode selection irvne ?internal read visibility/not e refer to 4.5 mode selection psel[3:0] ?priority select bit 4 through bit 0 can be written only while the i-bit in the ccr is set (interrupts disabled). these bits select one interrupt source to be elevated above all other i-bit related sources. table 8 cop timer rate selection rate period length cr[1:0] selected e = 1.0 mhz e = 2.0 mhz e = 3.0 mhz 0 0 2 15 ? e 32.768 ms 16.384 ms 10.923 ms 0 1 2 17 ? e 131.072 ms 65.536 ms 43.691 ms 1 0 2 19 ? e 524.288 ms 262.140 ms 174.76 ms 1 1 2 21 ? e 2.097 s 1.049 s 699.05 ms coprst arm/reset cop timer circuitry $103a bit 7 654321 bit 0 76543210 reset: 00010000 hprio highest priority i-bit interrupt and miscellaneous $103c bit 7 654321 bit 0 rboot* smod* mda* irvne psel3 psel2 psel1 psel0 reset: 00101 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC11EA9 motorola mc68HC11EA9ts/d 25 bits [7:4] ?not implemented always read zero nosec ?eeprom security mode disable refer to 4.10.3 eeprom security nocop ?cop system disable 0 = cop system enabled (forces reset on timeout) 1 = cop system disabled romon ?rom/eprom enable refer to 4 operating modes and on-chip memory . eeon ?eeprom enable refer to 4.10 eeprom table 9 highest i-bit interrupt source selection psel3 psel2 psel1 psel0 interrupt source promoted 0000 timer overflow 0001 pulse accumulator overflow 0010 pulse accumulator input edge 0011 reserved (default to irq ) 0100 sci serial system 0101 reserved (default to irq ) 0110 irq (external pin) 0111 real-time interrupt 1000 timer input capture 1 1001 timer input capture 2 1010 timer input capture 3 1011 timer output compare 1 1100 timer output compare 2 1101 timer output compare 3 1110 timer output compare 4 1111 timer ic4/oc5 psel[3:0] reset to %0101, making irq the highest priority i-bit related interrupt source. config security, cop, rom/eprom, and eeprom enables $103f bit 7 654321 bit 0 nosec nocop romon eeon reset: 00101 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68HC11EA9 26 mc68HC11EA9ts/d 6 parallel input/output the mc68hc(7)11ea9 has up to 36 input/output lines, depending on the operating mode. table 10 shows the configuration and features of each port. simple and full handshake input and output functions are available on ports b and c lines in single-chip mode. the following is a description of the handshake functions. in simple strobed mode, port b is a strobed output port and port c is a latching input port. the two ac- tivities are available simultaneously. the strb output is pulsed for two e-clock periods each time there is a write to the portb register. the invb bit in the pioc register controls the polarity of strb pulses. port c levels are latched into the alternate port c latch (portcl) register on each assertion of the stra input. stra edge select, flag, and interrupt enable bits are located in the pioc register. any or all of the port c lines can still be used as general-purpose i/o while in strobed input mode. full handshake modes involve port c pins and the stra and strb lines. input and output handshake modes are supported, and output handshake mode has a three-stated variation. stra is an edge de- tecting input, and strb is a handshake output. control and enable bits are located in the pioc register. in full input handshake mode, the mcu uses strb as a ready line to an external system. port c logic levels are latched into portcl when the stra line is asserted by the external system. the mcu then negates strb. the mcu reasserts strb after the portcl register is read. a mix of latched inputs, static inputs, and static outputs is allowed on port c, differentiated by the data direction bits and use of the portc and portcl registers. in full output handshake mode, the mcu writes data to portcl which, in turn, asserts the strb output to indicate that data is ready. the external system reads port c and asserts the stra input to acknowl- edge that data has been received. in the three-state variation of output handshake mode, lines intended as three-state handshake outputs are configured as inputs by clearing the corresponding ddrc bits. the mcu writes data to portcl and asserts strb. the external system responds by activating the stra input, which forces the mcu to drive the data in portcl out on all of the port c lines. the mode variation does not allow part of port c to be used for static inputs while other port c pins are being used for handshake outputs. refer to pioc register description for further information. table 10 i/o port configuration port input pins output pins bidirectional pins shared functions a 8 timer b 8 high order address c 8 multiplexed low order address/data d 2 sci/pll test e 8 a/d converter 1 xpin (xirq pin configured for data input) 1 ipin (irq pin configured for data input) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC11EA9 motorola mc68HC11EA9ts/d 27 staf ?strobe a interrupt status flag this bit is set when a selected edge occurs on strobe a. clearing it depends on the state of the hnds and oin bits. in simple strobed mode or in full handshake mode, staf is cleared by a read of the pioc register followed by a read of portcl register. in output handshake mode, staf is cleared by reading the pioc register followed by a write to portcl register. 0 = no edge detected on strobe a 1 = the selected edge (rising or falling) has been detected on strobe a stai ?strobe a interrupt enable when bit i in the condition code register is clear and stai is set, staf (when set) will request an inter- rupt. 0 = staf will not generate an interrupt when set. 1 = staf will generate an interrupt when set. cwom ?port c wire-or mode cwom affects all eight port a pins. 0 = port c outputs are normal cmos outputs 1 = port c outputs act as open-drain outputs hnds ?handshake mode when clear, strobe a acts as a simple input strobe to latch data into portcl, and strobe b acts as a simple output strobe which pulses after a write to port b. when set, a handshake protocol involving port c, stra, and strb is selected (see the definition for the oin bit). 0 = simple strobe mode 1 = full input or output handshake mode oin ?output or input handshaking this bit has no meaning or effect when hnds = 0. 0 = input handshake 1 = output handshake pls ?pulse/interlocked handshake operation this bit has no meaning if hnds = 0. when interlocked handshake operation is selected, strobe b, once activated, stays active until the selected edge of strobe a is detected. when pulsed handshake opera- tion is selected, strobe b is pulsed for two e cycles. 0 = interlocked handshake selected 1 = pulsed handshake selected ega ?active edge for strobe a 0 = falling edge of strobe a selected. when output handshake is selected, port c lines obey the data direction register while stra is low, but port c is forced to output when stra is high. 1 = rising edge of strobe a selected. when output handshake is selected, port c lines obey the data direction register while stra is high, but port c is forced to output when stra is low. invb ?invert strobe b 0 = active level is logic zero 1 = active level is logic one pioc port i/o control $1002 bit 7 654321 bit 0 staf stai cwom hnds oin pls ega invb reset: 00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68HC11EA9 28 mc68HC11EA9ts/d table 11 strobed and handshake parallel i/o control bit summary port pin function is mode dependent. do not confuse pin function with the electrical state of the pin at reset. port pins are either driven to a specified logic level or are configured as high impedance inputs. i/o pins configured as high-impedance inputs have port data that is indeterminate. the contents of the corresponding latches are dependent upon the electrical state of the pins during reset. in port descrip- tions, an "i" indicates this condition. port pins that are driven to a known logic level during reset are shown with a value of either one or zero. some control bits are unaffected by reset. reset states for these bits are indicated with a "u". note the timer forces the i/o state to output for each port a line associated with an en- abled output compare. in these cases the data direction bits will not be changed, but have no effect on these lines. the ddra will revert to controlling data direction when the associated timer compare is disabled. input captures do not force either the i/o state of the pin or the state of ddra. to enable pa3 as fourth input capture, set the i4/o5 bit in the pactl register. otherwise, pa3 is configured as a fifth out- put compare out of reset, with bit i4/o5 being cleared. if the dda3 bit in ddra is set (configuring pa3 as an output), and ic4 is enabled, writes to pa3 cause edges on the pin to result in input captures. writing to ti4/o5 has no effect when the ti4/ o5 register is acting as ic4. pa7 drives the pulse accumulator input but also can be configured for general-purpose i/o or output compare. dda7 bit in ddra reg- ister configures pa7 for either input or output. note that even when pa7 is config- ured as an output, the pin still drives the pulse accumulator input. porta port a data $1000 bit 7 654321 bit 0 pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 reset: iiiiiiii alt. pin func.: pai oc2 oc3 oc4 ic4/oc5 ic1 ic2 ic3 and/or oc1 oc1 oc1 oc1 oc1 1 0 0 1 0 1 port c driven stra active edge follow ddrc follow ddrc simple strobed mode full input handshake mode full output handshake mode 0 1 1 x 0 1 x 0 = strb active level read pioc with staf = 1 then read portcl read pioc with staf = 1 then read portcl read pioc with staf = 1 then write portcl 1 = strb active pulse 0 = strb active level 1 = strb active pulse staf clearing sequence hnds oin pls ega inputs latched into portcl on any active edge on stra driven as outputs if stra at active level; follows ddrc if stra not at active level strb pulses on writes to portb normal output port, unaffected in handshake modes normal output port, unaffected in handshake modes port c port b inputs latched into portcl on any active edge on stra f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC11EA9 motorola mc68HC11EA9ts/d 29 dda[7:0] ?data direction for port a 0 = corresponding pin configured for input 1 = corresponding pin configured for output ddb[7:0] ?data direction for port b 0 = corresponding pin configured for input 1 = corresponding pin configured for output portcl is used in the handshake clearing mechanism. when an active edge occurs on the stra pin, port c data is latched into the portcl register. reads of this register return the last value latched into portcl and clear staf flag (following a read of pioc with staf set). ddc[7:0] ?data direction for port c 0 = corresponding pin configured for input 1 = corresponding pin configured for output ddra port a data direction $1001 bit 7 654321 bit 0 dda7 dda6 dda5 dda4 dda3 dda2 dda1 dda0 reset: 00000000 portb port b data $1004 bit 7 654321 bit 0 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 reset: 00000000 alt. pin func.: addr15 addr14 addr13 addr12 addr11 addr10 addr9 addr8 ddrb port b data direction $1006 bit 7 654321 bit 0 ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 reset: 00000000 portc port c data $1003 bit 7 654321 bit 0 pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 reset: 00000000 alt. pin func.: addr7 addr6 addr5 addr4 addr3 addr2 addr1 addr0 or: data7 data6 data5 data4 data3 data2 data1 data0 portcl port c latched data $1005 bit 7 654321 bit 0 pcl7 pcl6 pcl5 pcl4 pcl3 pcl2 pcl1 pcl0 reset: 00000000 ddrc port c data direction $1007 bit 7 654321 bit 0 ddc7 ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 reset: 00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68HC11EA9 30 mc68HC11EA9ts/d xpin ?xirq interrupt pin status flag this is a read-only bit. xpin reflects the logic level present on the xirq pin. 0 = xirq pin low. 1 = xirq pin high. ipin ?irq interrupt pin status flag this is a read-only bit. ipin reflects the logic level present on the irq pin. 0 = irq pin low. 1 = irq pin high. xpin and ipin are read-only status bits that reflect the logic levels present on the xirq and irq pins. xpin and ipin provide the data bits that allow the xirq and irq pins to be used as general-purpose inputs. however, to use xirq and irq as data inputs, the interrupts normally generated by these two pins must be disabled with the disx and disi bits in the ddrd register. after reset pd[1:0] are configured as high-impedance inputs. pd[1:0] share functions with the sci sys- tem. 8 serial communications interface details information regarding port d sci functions. disx ?disable xirq pin interrupts can be read anytime. can be written only once. any write to the ddrd register will prevent modification of this bit. this bit must be set to use the xirq pin as a data input. 0 = interrupts generated by the xirq pin function are enabled 1 = interrupts generated by the xirq pin function are disabled disi ?disable irq pin interrupts can be read anytime. can be written only once. any write to the ddrd register will prevent modification of this bit. this bit must be set to use the irq pin as a data input. 0 = interrupts generated by the irq pin function are enabled 1 = interrupts generated by the irq pin function are disabled ddd[1:0] ?data direction for pd[1:0] 0 = corresponding port d pin configured for input 1 = corresponding port d pin configured for output port e has eight general-purpose input pins and shares functions with the a/d converter system. when any port e pins are being used as a/d inputs, porte should not be read during the sample portion of an a/d conversion. refer to 9 analog-to-digital converter for more information. portd port d data $1008 bit 7 654321 bit 0 xpin ipin pd1pd0 reset: 00000000 alt. pin func.: txdrxd ddrd port d data direction $1009 bit 7 654321 bit 0 disx disi ddd1 ddd0 reset: 00000000 porte port e data $100a bit 7 654321 bit 0 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 reset: iiiiiiii f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC11EA9 motorola mc68HC11EA9ts/d 31 7 timing system the timing system is based on a free-running 16-bit counter with a four-stage programmable prescaler. a timer overflow function allows software to extend the system? timing capability beyond the counter's 16-bit range. the main timer consists of the timer prescaler, the 16-bit free-running counter, and the capture/compare unit. 7.2 main timer details this portion of the timing system. the free-running counter can be driven by either the extal signal, as in other m68hc11 derivatives or it can be driven by a software-controlled phase-locked loop (pll) frequency synthesizer which has been added to the mc68hc(7)11ea9 mcus. the pll allows the mcu to operate in wait mode with extremely low power requirements. refer to 7.1 phase-locked loop synthesizer . in addition, the timing system includes pulse accumulator and real-time interrupt (rti) functions, as well as a clock monitor function, which can be used to detect clock failures that are not detected by the cop system. refer to the appropriate paragraphs within this section for information regarding these func- tions. table 12 shows a summary of the crystal-related frequencies and periods. table 12 timer summary control bits common system frequencies definition 4.0 mhz 8.0 mhz 12.0 mhz xtal 1.0 mhz 2.0 mhz 3.0 mhz e pr[1:0] main timer count rate (period length) 0 0 1 count 1000 ns 500 ns 333 ns 1/e overflow 65.536 ms 32.768 ms 21.845 ms 2 16 /e 0 1 1 count 4.0 m s 2.0 m s 1.333 m s 4/e overflow 262.14 ms 131.07 ms 32.768 ms 2 18 /e 1 0 1 count 8.0 m s 4.0 m s 2.667 m s 8/e overflow 524.28 ms 262.14 ms 174.76 ms 2 19 /e 1 1 1 count 16.0 m s 8.0 m s 5.333 m s 16/e overflow 1.049 s 524.29 ms 349.52 ms 2 20 /e rtr[1:0] periodic (rti) interrupt rates (period length) 0 0 8.192 ms 4.096 ms 2.731 ms 2 13 /e 0 1 16.384 ms 8.192 ms 5.461 ms 2 14 /e 1 0 32.768 ms 16.384 ms 10.923 ms 2 15 /e 1 1 65.536 ms 32.768 ms 21.845 ms 2 16 /e cr[1:0] cop watchdog timeout rates (period length) 0 0 32.768 ms 16.384 ms 10.923 ms 2 15 /e 0 1 131.072 ms 65.536 ms 43.691 ms 2 17 /e 1 0 524.288 ms 262.14 ms 174.76 ms 2 19 /e 1 1 2.098 s 1.049 s 699.05 ms 2 21 /e time-out tolerance (? ms/+...) 32.8 ms 16.4 ms 10.9 ms 2 15 /e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68HC11EA9 32 mc68HC11EA9ts/d 7.1 phase-locked loop synthesizer the phase-locked loop synthesizer (pll) generates clocks for the cpu, bus circuitry, and a/d convert- er. the clocks for the sci and timers are derived directly from the extal clock. the extal clock also provides the reference for the synthesizer which generates a frequency that is a multiple of the extal clock frequency. values written to the synr register determine the factor by which the extal clock is scaled. refer to figure 8 . the pll has two frequency bandwidths which are automatically selected whenever auto = 1 in the pllcr register. when the pll is first enabled, the wide bandwidth is selected to provide a fast ramp time. when the desired frequency is nearly reached, the low bandwidth is selected to provide greater stability. manual control of bandwidth can be accomplished by clearing the auto bit. figure 8 phase-locked loop synthesizer block diagram ea9 pll block crystal oscillator synr loop filter vco bus clock select extal 4xclk for cpu and memories module clock select pllmo for sci and timer mcs v ddsyn ? sci clock ? synchronize with ph2 timer clock to timer prescaler pllto ? ph2 e extal pin 0 = extal 1 = 4xclk bcs 0 = extal 1 = vcout vcout 2(y + 1) ?2 x ) y = syny[1:0] x = synx[5:0] xfc pin xtal pin frequency divider phase detect vcout pcomp extal to sci modulus baud generator sci baud clock phase-locked loop synthesizer external crystal v ddsyn pin xfc f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC11EA9 motorola mc68HC11EA9ts/d 33 pllon ?pll system enable this bit activates the pll synthesizer circuit without connecting its output to the control circuit. this al- lows the synthesizer to stabilize before it can drive the cpu clocks. this bit resets to one, allowing the synthesizer to stabilize as the device is being powered up. 0 = pll is off 1 = pll is on bcs ?bus clock select this bit determines which signal drives the clock circuitry generating the bus clocks. refer to figure 8 . once bcs has been changed, up to 1.5 extal cycles + 1.5 pllout cycles may be required for the transition. during the transition, all cpu activity will cease. bcs is cleared by a stop or wait instruc- tion or when v ddsyn falls to the v ss level. 0 = extal drives the clock circuit 1 = vcout drives the clock circuit note pllon and bcs have built-in protection such that the pll cannot be selected to drive any clocks if the pll is off. similarly, the pll cannot be turned off if it has been selected as a clock source. turning the pll on and selecting its output as a clock source require two separate writes to the pllcr register. auto ?automatic/manual loop filter bandwidth control this bit selects between automatic bandwidth control circuits within the phase detect block and manual bandwidth control. refer to table 13 . 0 = automatic bandwidth control is selected 1 = bandwidth control is manual bwc ?loop filter bandwidth control/status bandwidth control is manual only when auto = 0. since the low bandwidth driver is always enabled, bwc determines if the high bandwidth driver is enabled. when auto = 1, bwc is a read-only status bit that indicates which mode has been selected by the internal circuit. during pll start-up in automatic mode, the high bandwidth driver is enabled by internal circuitry until the pll is near the selected fre- quency. the high bandwidth driver is then disabled and bwc is cleared. refer to table 13 . 0 = only the low bandwidth driver is enabled 1 = both low and high bandwidth drivers are selected vcot ?voltage controlled oscillator (vco) test this bit is used to isolate the loop filter from the vco to aid in factory testing of the pll. vcot is always set when auto = 1 (automatic bandwidth control mode). this bit can be written only in special test mode. 0 = loop filter low bandwidth mode is disabled (factory test only) 1 = loop filter operates according to values of auto and bwc control bits pllcr pll control $1036 bit 7 654321 bit 0 pllon bcs auto bwc vcot mcs lck wen reset: 10111000 table 13 loop filter bandwidth driver control auto bwc vcot high bandwidth driver low bandwidth driver 0 0 0 off off 0 0 1 off on 0 1 0 on off 0 1 1 on on 1 x 1 automatic on f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68HC11EA9 34 mc68HC11EA9ts/d mcs ?module clock select this bit determines which clock signal drives the sci and timer. 0 = extal is the clock source for sci and timer divider chains 1 = 4xclk is the clock source for the sci and timer divider chains lck?synthesizer lock detect flag this is a read-only status bit that indicates when the pll has stabilized. bcs cannot be set (selecting vcout as a clock source) until lck is set. 0 = the pll is not stable 1 = the pll has stabilized wen ?wait enable this bit determines whether the extal signal will be used to drive the cpu clocks while the device is in wait mode. when this feature is enabled, entering wait mode clears bcs (selecting extal as the source for cpu clocks) and reduces the pll frequency to the lowest value, modulus 1. any interrupt or reset or the assertion of the raf bit within the sci (if the receiver is enabled by re = 1) will allow the pll to resume operation at the frequency selected in synr register. then the user must set bcs to select vcout as the source for cpu clocks. 0 = vcout remains connected to the 4xclk circuit during operation in wait mode. 1 = after stacking prior to entering wait mode, bcs is cleared and the pll is maintained at the lowest frequency available (modulus 1). this register resets to $06 for a preset multiplication factor of 14. synx[1:0] ?binary tap select bits these two bits select one of four binary taps. synx[1:0] affect the frequency multiplication factor, vari- able x according to the formula below. syny[5:0] ?modulo counter rate select bits these six bits select one of 64 binary values that affect the frequency multiplication factor, variable y according to the formula below. where x = the value represented by bits synx[1:0] y = the value represented by bits syny[5:0] 7.2 main timer the main timer consists of the timer prescaler, the free-running counter, and the capture/compare unit. the timer prescaler selects one of four division rates and drives the free-running 16-bit counter. the capture/compare unit has three channels for input capture, four channels for output compare, and one channel that can be configured as a fourth input capture or a fifth output compare. timer channels con- figured for input capture (icx) cause the current value of the free-running counter to be latched into an input capture register (ticx) when a pulse edge is detected on the corresponding pin. channels con- figured for output compare allow a pulse to be output when the free-running counter matches a value loaded into an output compare register (tocx). figure 9 shows a detailed block diagram of the timer prescaler and the capture/compare unit. synr frequency synthesizer control $1037 bit 7 654321 bit 0 synx1 synx0 syny5 syny4 syny3 syny2 syny1 syny0 reset: 00000110 2y1 + () 2 x () f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC11EA9 motorola mc68HC11EA9ts/d 35 figure 9 main timer block diagram ea9 cc block pllto * (pllmo ?4) 16-bit latch clk pa0/ic3 4 3 5 6 7 8 2 1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 port a pin control oc1i oc2i oc3i oc4i i4/o5i ic1i ic2i ic3i tflg1 status flags foc1 foc2 foc3 foc4 foc5 oc1f oc2f oc3f oc4f i4/o5f ic1f ic2f ic3f pa1/ic2 pa2/ic1 pa3/oc5/ ic4/oc1 pa4/oc4/ oc1 pa5/oc3/ oc1 pa6/oc2/ oc1 pa7/oc1/ pai i4/o5 16-bit comparator toc1 (hi) toc1 (lo) = 16-bit comparator toc2 (hi) toc2 (lo) = 16-bit comparator toc3 (hi) toc3 (lo) = 16-bit comparator toc4 (hi) toc4 (lo) = 16-bit latch tic1 (hi) tic1 (lo) clk 16-bit latch tic2 (hi) tic2 (lo) clk 16-bit latch tic3 (hi) tic3 (lo) clk 16-bit comparator ti4/o5 (hi) ti4/o5 (lo) = 16-bit free running counter tcnt (hi) tcnt (lo) 9 toi tof interrupt requests (further qualified by i bit in ccr) taps for rti, cop watchdog, and pulse accumulator prescaler divide by 1, 4, 8, or 16 pr1 pr0 16-bit timer bus oc5 ic4 to pulse accumulator tmsk1 interrupt enables cforc force output compare pin functions * refer to pll block diagram. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68HC11EA9 36 mc68HC11EA9ts/d foc[1:5] ?force output compare write ones to force compare(s) 0 = not affected 1 = output x action occurs bits [2:0] ?not implemented always read zero set bit(s) to enable oc1 to control corresponding port a pin(s). if oc1mx is set, data in oc1dx is output on port a pin x upon successful oc1 compares. bits [2:0] ?not implemented always read zero set bit(s) to enable oc1 to control corresponding port a pin(s). if oc1mx is set, data in oc1dx is output to port a bit x on successful oc1 compares. bits [2:0] ?not implemented always read zero tcnt resets to $0000. in normal modes (smod = 0), tcnt is a read-only register. ticx is not affected by reset. cforc timer compare force $100b bit 7 654321 bit 0 foc1 foc2 foc3 foc4 foc5 reset: 00000000 oc1m output compare 1 mask $100c bit 7 654321 bit 0 oc1m7 oc1m6 oc1m5 oc1m4 oc1m3 reset: 00000000 oc1d output compare 1 data $100d bit 7 654321 bit 0 oc1d7 oc1d6 oc1d5 oc1d4 oc1d3 reset: 00000000 tcnt timer counter $100e?100f bit 15 14 13 12 11 10 9 bit 8 tcnt (hi) bit 7 654321 bit 0 tcnt (lo) tic1?ic3 timer input capture $1010?1015 $1010 bit 15 14 13 12 11 10 9 bit 8 tic1 (hi) $1011 bit 7 654321 bit 0 tic1 (lo) $1012 bit 15 14 13 12 11 10 9 bit 8 tic2 (hi) $1013 bit 7 654321 bit 0 tic2 (lo) $1014 bit 15 14 13 12 11 10 9 bit 8 tic3 (hi) $1015 bit 7 654321 bit 0 tic3 (lo) f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC11EA9 motorola mc68HC11EA9ts/d 37 all tocx register pairs reset to $ffff. this is a shared register and is either input capture 4 or output compare 5 depending on the state of bit i4/o5 in pactl. writes to ti4/o5 have no effect when this register is configured as input capture 4. the ti4/o5 register pair resets to $ffff. toc1?oc4 timer output compare $1016?101d $1016 bit 15 14 13 12 11 10 9 bit 8 toc1 (hi) $1017 bit 7 654321 bit 0 toc1 (lo) $1018 bit 15 14 13 12 11 10 9 bit 8 toc2 (hi) $1019 bit 7 654321 bit 0 toc2 (lo) $101a bit 15 14 13 12 11 10 9 bit 8 toc3 (hi) $101b bit 7 654321 bit 0 toc3 (lo) $101c bit 15 14 13 12 11 10 9 bit 8 toc4 (hi) $101d bit 7 654321 bit 0 toc4 (lo) ti4/o5 timer input capture 4/output compare 5 $101e?101f bit 15 14 13 12 11 10 9 bit 8 tcnt (hi) bit 7 654321 bit 0 tcnt (lo) tctl1 timer control 1 $1020 bit 7 654321 bit 0 om2 ol2 om3 ol3 om4 ol4 om5 ol5 reset: 00000000 table 14 output compare channel configuration omx olx action on successful compare 0 0 none ?output compare channel (ocx) disabled 0 1 toggle ocx output pin logic level 1 0 drive ocx output pin low 1 1 drive ocx output pin high tctl2 timer control 2 $1021 bit 7 654321 bit 0 edg4b edg4a edg1b edg1a edg2b edg2a edg3b edg3a reset: 00000000 table 15 input capture channel configuration edgxb edgxa input capture configuration 0 0 input capture channel (icx) disabled 0 1 capture on rising edge on icx input pin 1 0 capture on falling edge on icx input pin 1 1 capture on any edge on icx input pin f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68HC11EA9 38 mc68HC11EA9ts/d oc1i?c4i ?output compare (ocx) interrupt enable if the ocxi enable bit is set when a match occurs, an interrupt is generated. 0 = interrupts from ocx channel disabled 1 = successful compares on ocx channel generate interrupts i4/o5i ?input capture 4/output compare 5 interrupt enable when i4/o5 in pactl is one, i4/o5i is the input capture 4 interrupt enable bit and edges on the i4/o5 pin generate interrupts. when i4/o5 in pactl is zero, i4/o5i is the output compare 5 interrupt enable bit and successful matches generate interrupts. 0 = interrupts from ic4/oc5 channel disabled 1 = interrupts from ic4/oc5 channel enabled ic1i?c3i ?input capture (icx) interrupt enable if the icxi enable bit is set when an edge is detected on the icx pin, an interrupt is generated. 0 = interrupts from icx channel disabled 1 = edges detected on icx pin generate interrupts note bits in tmsk1 correspond bit for bit with flag bits in tflg1. ones in tmsk1 enable the corresponding interrupt sources. clear a flag by writing a one to the appropriate bit. oc1f?c4f ?output compare (ocx) interrupt flag if the ocxi enable bit is set when a match occurs, the corresponding flag bit is set and an interrupt is generated. 0 = no match has occurred 1 = a successful compare has occurred on ocx channel i4/o5i ?input capture 4/output compare 5 interrupt enable when i4/o5 in pactl is one, i4/o5i is the input capture 4 interrupt enable bit and edges (rising or fall- ing, depending on configuration) on the i4/o5 pin cause this flag to be set and an interrupt is generated. when i4/o5 in pactl is zero, i4/o5i is the output compare 5 interrupt enable bit and successful match- es cause this flag to be set and an interrupt generated. 0 = interrupts from ic4/oc5 channel disabled 1 = interrupts from ic4/oc5 channel enabled ic1i?c3i ?input capture (icx) interrupt enable if the icxi enable bit is set when an edge (rising or falling, depending on configuration) is detected on the icx pin, an interrupt is generated. 0 = interrupts from icx channel disabled 1 = edges detected on icx pin generate interrupts tmsk1 timer interrupt mask 1 $1022 bit 7 654321 bit 0 oc1i oc2i oc3i oc4i i4/o5i ic1i ic2i ic3i reset: 00000000 tflg1 timer interrupt flag 1 $1023 bit 7 654321 bit 0 oc1f oc2f oc3f oc4f i4/o5f ic1f ic2f ic3f reset: 00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC11EA9 motorola mc68HC11EA9ts/d 39 bits [7:4] can be written at any time. pr[1:0] can only be written once in the first 64 cycles after reset in normal modes (smod = 0). in special modes (smod = 1) pr[1:0] can be written any time. toi ?timer overflow interrupt enable if the toi enable bit is set when the value in the timer counter register (tcnt) changes from $ffff to $0000, an interrupt is generated. 0 = timer overflow interrupts disabled 1 = interrupts are generated each time tcnt rolls over to $0000 rtii ?real-time interrupt enable if rtii enable bit is set, interrupts are generated at the rate determined by the real-time interrupt rate (rtr[1:0]) bits in pactl. 0 = periodic interrupts are disabled 1 = interrupts are generated at the rate determined by rtr[1:0] paovi ?pulse accumulator overflow interrupt enable if the paovi enable bit is set when the pulse accumulator counter register (pacnt) changes from $ffff to $0000 an interrupt is generated. 0 = pcnt overflow interrupts are disabled 1 = interrupts are generated each time pcnt rolls over to $0000 paii ?pulse accumulator input edge interrupt enable if the paii enable bit is set when an edge (rising or falling, depending on configuration) is detected on the pulse accumulator input pin (pa7/pai), an interrupt is generated. 0 = interrupts from edges on pai pin are disabled 1 = edges detected on pai pin generate interrupts (rising or falling, depending on configuration) bits [3:2] ?not implemented always read zero pr[1:0] ?timer prescaler select tmsk2 timer interrupt mask 2 $1024 bit 7 654321 bit 0 toi rtii paovi paii pr1 pr0 reset: 00000000 table 16 main timer prescaler selection pr1 pr0 prescaler selected 00 ? 1 01 ? 4 10 ? 8 11 ? 16 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68HC11EA9 40 mc68HC11EA9ts/d tof ?timer overflow interrupt flag if the toi enable bit is set when the timer counter register (tcnt) changes from $ffff to $0000, this flag is set and an interrupt is generated. 0 = tcnt has not rolled over since either the tof flag bit was last cleared or the toi enable bit was set. 1 = tcnt has rolled over to $0000 rtif ?real-time interrupt flag if rtii enable bit is set, this flag is set and an interrupt is generated periodically at the rate determined by the real-time interrupt rate (rtr[1:0]) bits in pactl. 0 = no periodic interrupt has occurred since either the rtif flag bit was last cleared or when the rtii enable bit was set 1 = a periodic interrupt has occurred paovf ?pulse accumulator overflow interrupt flag if the paovi enable bit is set when the pulse accumulator counter register (pcnt) rolls over to $0000, this flag is set and an interrupt is generated. 0 = pcnt has not rolled over since either the paovf flag bit was last cleared or the paovi enable bit was set. 1 = pcnt has rolled over to $0000 paif ?pulse accumulator input edge interrupt flag if the paii enable bit is set when an edge is detected on the pulse accumulator input pin (pa7/pai), this flag is set and an interrupt is generated. 0 = no edge has been detected on the pai pin 1 = an edge (rising or falling, depending on configuration) has been detected on the pai pin bits [3:0] ?not implemented always read zero bits [7:4] can be written at any time. pr[1:0] can only be written once in the first 64 cycles after reset in normal modes (smod = 0). in special modes (smod = 1) pr[1:0] can be written any time. bit 7 ?not implemented always reads zero paen ?pulse accumulator enable refer to 7.4 pulse accumulator . pamod ?pulse accumulator mode select refer to 7.4 pulse accumulator . pedge ?pulse accumulator input edge select refer to 7.4 pulse accumulator . tflg2 timer interrupt flag 2 $1025 bit 7 654321 bit 0 tof rtif paovf paif reset: 00000000 pactl pulse accumulator control $1026 bit 7 654321 bit 0 paen pamod pedge i4/o5 rtr1 rtr0 reset: 00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC11EA9 motorola mc68HC11EA9ts/d 41 bit 3 ?not implemented always reads zero i4/o5 ?input capture 4/output compare 5 select 0 = interrupts from edges on pai pin are disabled 1 = edges detected on pai pin generate interrupts (rising or falling, depending on configuration) rtr[1:0] ?real-time interrupt rate select adpu ?a/d converter power up refer to 9 analog-to-digital converter csel ?clock select 0 = a/d and eeprom use the system e clock 1 = a/d and eeprom use internal rc clock irqe ?irq select edge-sensitive only refer to 5 resets and interrupts dly ?enable oscillator start-up delay 0 = no stabilization delay on exit from stop mode. 1 = a delay of approximately 4000 e-clock cycles is imposed as the mcu exits stop mode. cme ?clock monitor enable 0 = clock monitor disabled; slow clock can be used. 1 = slow or stopped clocks cause cop failure reset. bit 2 ?not implemented always reads zero cr[1:0] ?cop timer rate select refer to 5 resets and interrupts table 17 real-time interrupt rates rate rti rate selected rtr[1:0] selected e = 1.0 mhz e = 2.0 mhz e = 3.0 mhz 0 0 2 13 ? e 8.192 ms 4.096 ms 2.731 ms 0 1 2 14 ? e 16.384 ms 8.192 ms 5.461 ms 1 0 2 15 ? e 32.768 ms 16.384 ms 10.923 ms 1 1 2 16 ? e 65.536 ms 32.768 ms 21.845 ms option system configuration options $1039 bit 7 654321 bit 0 adpu csel irqe* dly* cme cr1* cr0* reset: 00010000 * can be written only once in first 64 cycles after reset in normal modes, or at any time in special modes. table 18 cop timer rate selection cr[1:0] rate selected period length e = 1.0 mhz e = 2.0 mhz e = 3.0 mhz 0 0 2 15 ? e 32.768 ms 16.384 ms 10.923 ms 0 1 2 17 ? e 131.072 ms 65.536 ms 43.691 ms 1 0 2 19 ? e 524.288 ms 262.140 ms 174.76 ms 1 1 2 21 ? e 2.097 s 1.049 s 699.05 ms f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68HC11EA9 42 mc68HC11EA9ts/d 7.3 real-time interrupt the real-time interrupt (rti) function can generate interrupts at different fixed periodic rates. these rates are a function of the mcu oscillator frequency and the value of the software-accessible control bits, rtr1 and rtr0. these bits determine the rate at which interrupts are requested by the rti sys- tem. the rti system is driven by an e divided by 2 13 rate clock compensated so that it is independent of the timer prescaler. the rtr1 and rtr0 control bits select an additional division factor. rti is set to its fastest rate by default out of reset and can be changed at any time. tof ?timer overflow interrupt flag refer to 7.2 main timer rtif ?real-time interrupt flag if rtii enable bit is set, this flag is set and an interrupt is generated periodically at the rate determined by the real-time interrupt rate (rtr[1:0]) bits in pactl. 0 = no periodic interrupt has occurred since either the rtif flag bit was last cleared or the rtii enable bit was set 1 = a periodic interrupt has occurred paovf ?pulse accumulator overflow interrupt flag refer to 7.4 pulse accumulator paif ?pulse accumulator input edge interrupt flag refer to 7.4 pulse accumulator bits [3:0] ?not implemented always read zero table 19 real-time interrupt rates (period length) period length period length rtr[1:0] selected e = 1.0 mhz e = 2.0 mhz e = 3.0 mhz 0 0 2 13 ? e 8.192 ms 4.096 ms 2.731 ms 0 1 2 14 ? e 16.384 ms 8.192 ms 5.461 ms 1 0 2 15 ? e 32.768 ms 16.384 ms 10.923 ms 1 1 2 16 ? e 65.536 ms 32.768 ms 21.845 ms table 20 real-time interrupt rates (frequency) maximum maximum interrupt frequency rtr[1:0] frequency possible e = 1.0 mhz e = 2.0 mhz e = 3.0 mhz 0 0 2 13 ? e 122.070 hz 244.141 hz 366.211 hz 0 1 2 14 ? e 61.035 hz 122.070 hz 183.105 hz 1 0 2 15 ? e 30.518 hz 61.035 hz 91.553 hz 1 1 2 16 ? e 15.258 hz 30.518 hz 45.776 hz tflg2 timer interrupt flag 2 $1025 bit 7 654321 bit 0 tof rtif paovf paif reset: 00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC11EA9 motorola mc68HC11EA9ts/d 43 bits [7:4] can be written at any time. pr[1:0] can only be written once in the first 64 cycles after reset in normal modes (smod = 0). in special modes (smod = 1) pr[1:0] can be written any time. bit 7 ?not implemented always reads zero paen ?pulse accumulator enable refer to 7.4 pulse accumulator pamod ?pulse accumulator mode select refer to 7.4 pulse accumulator pedge ?pulse accumulator input edge select refer to 7.4 pulse accumulator bit 3 ?not implemented always reads zero i4/o5 ?input capture 4/output compare 5 select refer to 7.2 main timer rtr[1:0] ?real-time interrupt rate select 7.4 pulse accumulator m68hc11-family mcus have an 8-bit counter within the timing system that can be configured for event counting or for gated time accumulation. the counter (pacnt) can be read or written at any time. the port a bit 7 i/o pin can be configured to act as a clock in event counting mode and edges on the pulse accumulator input pin cause the counter (pacnt) to increment. when the pulse accumulator is configured for time accumulation, an edge on the pulse accumulator input pin enables a free-running clock (e divided by 64) that drives pacnt in gated time accumulation mode. refer to figure 10 . pactl pulse accumulator control $1026 bit 7 654321 bit 0 paen pamod pedge i4/o5 rtr1 rtr0 reset: 00000000 table 21 real-time interrupt rates rate rti rate selected rtr[1:0] selected e = 1.0 mhz e = 2.0 mhz e = 3.0 mhz 0 0 2 13 ? e 8.192 ms 4.096 ms 2.731 ms 0 1 2 14 ? e 16.384 ms 8.192 ms 5.461 ms 1 0 2 15 ? e 32.768 ms 16.384 ms 10.923 ms 1 1 2 16 ? e 65.536 ms 32.768 ms 21.845 ms f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68HC11EA9 44 mc68HC11EA9ts/d figure 10 pulse accumulator block diagram bits [7:4] can be written at any time. pr[1:0] can only be written once in the first 64 cycles after reset in normal modes (smod = 0). in special modes (smod = 1) pr[1:0] can be written any time. bit 7 ?not implemented always reads zero paen ?pulse accumulator enable 0 = periodic interrupts are disabled 1 = interrupts are generated at the rate determined by rtr[1:0] pamod ?pulse accumulator mode select 0 = pcnt overflow interrupts are disabled 1 = interrupts are generated each time pcnt rolls over to $0000 pactl pulse accumulator control $1026 bit 7 654321 bit 0 paen pamod pedge i4/o5 rtr1 rtr0 reset: 00000000 ea9 pls acc block pedge pamod paen pactl control internal data bus pacnt 8-bit counter pa7/ pai/ oc1 interrupt requests paif paovf tflg2 interrupt status paovi paii paovf paovi paif paii tmsk2 int enables 1 2 overflow enable disable flag setting clock pai edge paen paen 2 : 1 mux output buffer input buffer and edge detector from main timer oc1 data bus mcu pin pllto ? 64 clock * (from main timer) from data direction bit for port a pin 7 * refer to timer and pll block diagrams. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC11EA9 motorola mc68HC11EA9ts/d 45 pedge ?pulse accumulator input edge select 0 = interrupts from edges on pai pin are disabled 1 = edges detected on pai pin generate interrupts (rising or falling, depending on configuration) bit 3 ?not implemented always reads zero i4/o5 ?input capture 4/output compare 5 select refer to 7.2 main timer . rtr[1:0] ?timer prescaler select refer to 7.3 real-time interrupt . bits [7:4] can be written at any time. pr[1:0] can only be written once in the first 64 cycles after reset in normal modes (smod = 0). in special modes (smod = 1) pr[1:0] can be written any time. toi ?timer overflow interrupt enable refer to 7.2 main timer . rtii ?real-time interrupt enable refer to 7.3 real-time interrupt . paovi ?pulse accumulator overflow interrupt enable if the paovi enable bit is set when the pulse accumulator counter register (pacnt) changes from $ffff to $0000 an interrupt is generated. 0 = pcnt overflow interrupts are disabled 1 = interrupts are generated each time pcnt rolls over to $0000 paii ?pulse accumulator input edge interrupt enable if the paii enable bit is set when an edge (rising or falling, depending on configuration) is detected on the pulse accumulator input pin (pa7/pai), an interrupt is generated. 0 = interrupts from edges on pai pin are disabled 1 = edges detected on pai pin generate interrupts (rising or falling, depending on configuration) bits [3:2] ?not implemented always read zero pr[1:0] ?timer prescaler select refer to 7.2 main timer . pacnt pulse accumulator counter $1027 bit 7 654321 bit 0 bit 7 654321 bit 0 can be read and written, unaffected by reset. tmsk2 timer interrupt mask 2 $1024 bit 7 654321 bit 0 toi rtii paovi paii pr1 pr0 reset: 00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68HC11EA9 46 mc68HC11EA9ts/d tof ?timer overflow interrupt flag refer to 7.2 main timer . rtif ?real-time interrupt flag refer to 7.3 real-time interrupt . paovf ?pulse accumulator overflow interrupt flag if the paovi enable bit is set when the pulse accumulator counter register (pcnt) rolls over to $0000, this flag is set and an interrupt is generated. 0 = pcnt has not rolled over since either the paovf flag bit was last cleared or when the paovi enable bit was set. 1 = pcnt has rolled over to $0000 paif ?pulse accumulator input edge interrupt flag if the paii enable bit is set when an edge is detected on the pulse accumulator input pin (pa7/pai), this flag is set and an interrupt is generated. 0 = no edge has been detected on the pai pin 1 = an edge (rising or falling, depending on configuration) has been detected on the pai pin bits [3:0] ?not implemented always read zero tflg2 timer interrupt flag 2 $1025 bit 7 654321 bit 0 tof rtif paovf paif reset: 00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC11EA9 motorola mc68HC11EA9ts/d 47 8 serial communications interface the sci, a universal asynchronous receiver transmitter (uart) serial communications interface, is an independent serial i/o subsystem in mc68hc(7)11ea9 mcus. the registers and control bits used in previous m68hc11 sci systems have been rearranged and new features added. new or enhanced fea- tures include the following: ?a 13-bit modulus prescaler that allows greater baud rate control ?a new idle mode detect, independent of preceding serial data ?a receiver active flag ?hardware parity for both transmitter and receiver the enhanced baud rate generator is shown in the following diagram. refer to the table of sci baud rate control values for standard values. figure 11 sci baud generator circuit diagram 13-bit counter 13-bit compare scbdh/l sci baud control internal phase 2 clock (ph2) = 2 synchronize with ph2 16 receiver baud rate clock transmitter baud rate clock sci baud clock extal ?2, if mcs = 0 4xclk ?2, if mcs = 1 reset ea9 baud gen bloc k f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68HC11EA9 48 mc68HC11EA9ts/d figure 12 sci transmitter block diagram ea9 sci tx block fe nf or idle rdrf tc tdre scsr1 sci status 1 sbk rwu re te ilie rie tcie tie sccr2 sci control 2 transmitter control logic tcie tc tie tdre sci rx requests sci interrupt request internal data bus pin buffer and control h(8)76543210l 10 (11) - bit tx shift register ddd1 pd1 txd scdrl tx/rx data low transfer tx buffer shift enable jam enable preamble?am 1s break?am 0s (write only) force pin direction (out) size 8/9 wake m loops sccr1 sci control 1 transmitter clock (from modulus baud rate generator) parity generator ilt pe pt scdrh tx/rx data high 0 1 2 3 4 5 6 7 r8 t8 $x076 $x077 woms pf f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC11EA9 motorola mc68HC11EA9ts/d 49 figure 13 sci receiver block diagram ea9 sci rx blo c scdrl tx/rx data low scdrh tx/rx data high 0 1 2 3 4 5 6 7 r8 t8 $x07 6 $x07 7 fe nf or idle rdrf tc tdre scsr1 sci status 1 sbk rwu re te ilie rie tcie tie sccr2 sci control 2 wake m woms loops wakeup logic rie or ilie idle sci tx requests sci interrupt request internal data bus pin buffer and control ddd0 pd0 rxd stop (8)76543210 10 (11) - bit rx shift register (read only) sccr1 sci control 1 rie rdrf start msb all ones data recovery ?6 rwu m re (disables pin driver) receiver clock (from modulus baud rate generator) ilt pe pt parity detect pf raf scsr2 sci status 2 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68HC11EA9 50 mc68HC11EA9ts/d btst ?baud register test (test) factory test only bspl ?baud rate counter split (test) factory test only bit 5 ?not implemented always reads zero sbr[12:0] ?sci baud rate select bits use the following formula to calculate sci baud rate. refer to the table of baud rate control values for example rates: sci baud rate = extal ? (32 ?br) where br is the contents of sbr[12:0] in scbdh,l (br = 1, 2, 3 ... 8191 decimal, or br = $0001, $0002, $0003 ... $1fff hexadecimal) br = 0 disables the baud rate generator. scbdh, scbdl sci baud rate select high, sci baud rate select low $1028, $1029 bit 7 654321 bit 0 $1028 btst bspl sbr12 sbr11 sbr10 sbr9 sbr8 high reset: 00000000 $1029 sbr7 sbr6 sbr5 sbr4 sbr3 sbr2 sbr1 sbr0 low reset: 00000100 table 22 baud rate selection target crystal frequency (xtal) baud 8 mhz 12 mhz 16 mhz rate dec value hex value dec value hex value dec value hex value 110 2272 $08e0 3409 $0d51 4545 $11c1 312 156 78 2500 $09c4 3333 $0d05 300 833 $0341 1250 $04e2 1666 $0682 600 416 $01a0 625 $0271 833 $0341 1200 208 $00d0 312 $0138 416 $01a0 2400 104 $0068 156 $009c 208 $00d0 4800 52 $0034 78 $004e 104 $0068 9600 26 $001a 39 $0027 52 $0034 19.2k 13 $000d 20 $0014 26 $001a 38.4k 13 $000d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC11EA9 motorola mc68HC11EA9ts/d 51 loops ?sci loop mode enable 0 = sci transmit and receive operate normally 1 = sci transmit and receive are disconnected from txd and rxd pins, and transmitter output is fed back into the receiver input woms ?wired-or mode option for pd[1:0] (see also dwom bit in spcr.) 0 = txd and rxd operate normally 1 = txd and rxd are open drains if operating as an output bit 5 ?not implemented always reads zero m ?mode (select character format) 0 = start, 8 data bits, 1 stop bit 1 = start, 9 data bits, 1 stop bit wake ?wake-up by address mark/idle 0 = wake-up by idle line recognition 1 = wake-up by address mark (most significant data bit set) ilt ?idle line type 0 = short (sci counts consecutive ones after start bit) 1 = long (sci counts ones only after stop bit) pe ?parity enable 0 = parity disabled 1 = parity enabled pt ?parity type 0 = parity even (even number of ones causes parity bit to be zero, odd number of ones causes par- ity bit to be one) 1 = parity odd (odd number of ones causes parity bit to be zero, even number of ones causes parity bit to be one) tie ?transmit interrupt enable 0 = tdre interrupts disabled 1 = sci interrupt requested when tdre status flag is set tcie ?transmit complete interrupt enable 0 = tc interrupts disabled 1 = sci interrupt requested when tc status flag is set rie ?receiver interrupt enable 0 = rdrf and or interrupts disabled 1 = sci interrupt requested when rdrf flag or the or status flag is set sccr1 sci control register 1 $102a bit 7 654321 bit 0 loops woms m wake ilt pe pt reset: 00000000 sccr2 sci control register 2 $102b bit 7 654321 bit 0 tie tcie rie ilie te re rwu sbk reset: 00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68HC11EA9 52 mc68HC11EA9ts/d ilie ?idle line interrupt enable 0 = idle interrupts disabled 1 = sci interrupt requested when idle status flag is set te ?transmitter enable 0 = transmitter disabled 1 = transmitter enabled re ?receiver enable 0 = receiver disabled 1 = receiver enabled rwu ?receiver wake-up control 0 = normal sci receiver 1 = wake-up enabled and receiver interrupts inhibited sbk ?send break 0 = break generator off 1 = break codes generated as long as sbk = 1 tdre ?transmit data register empty flag set if transmit data can be written to scdr; if tdre = 0, transmit data register is busy. cleared by scsr1 read with tdre set, followed by scdr write. 0 = transmit data register contains data and is busy 1 = transmit data register is empty and scdr can be written tc ?transmit complete flag set if transmitter is idle (no data, preamble, or break transmission in progress). cleared by scsr1 read with tc set, followed by scdr write. 0 = transmitter is busy 1 = transmitter is idle and scdr can be written rdrf ?receive data register full flag set if a received character is ready to be read from scdr. cleared by scsr1 read with rdrf set, followed by scdr read. idle ?idle line detected flag once cleared, idle is set again until the rxd line has been active and becomes idle once more. idle flag is inhibited when rwu = 1. set if the rxd line is idle. cleared by scsr1 read with idle set, fol- lowed by scdr read. or ?overrun error flag set if a new character is received before a previously received character is read from scdr. cleared by scsr1 read with or set, followed by scdr read. nf ?noise error flag set if majority sample logic detects anything other than a unanimous decision. cleared by scsr1 read with nf set, followed by scdr read. fe ?framing error set if a zero is detected where a stop bit was expected. cleared by scsr1 read with fe set, followed by scdr read. scsr1 sci status register 1 $102c bit 7 654321 bit 0 tdre tc rdrf idle or nf fe pf reset: 00000000 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC11EA9 motorola mc68HC11EA9ts/d 53 pf ?parity error flag set if received data has incorrect parity. cleared by scsr1 read with pe set, followed by scdr read. bits [7:1] ?not implemented always read zero raf ?receiver active flag (read only) 0 = the receiver circuitry is idle 1 = a character is being received r8 ?receiver bit 8 ninth serial data bit received when sci is configured for nine data bit operation (m = 1). t8 ?transmitter bit 8 ninth serial data bit transmitted when sci is configured for nine data bit operation (m = 1). bits [5:0] ?not implemented always read zero r/t[7:0] ?receiver/transmitter data bits 7 to 0 sci data is double buffered in both directions. scsr2 sci status register 2 $102d bit 7 654321 bit 0 raf reset: 00000000 scdrh, scdrl sci data high, sci data low $102e, $102f bit 7 654321 bit 0 $102e r8 t8 high $102f r7/t7 r6/t6 r5/t5 r4/t4 r3/t3 r2/t2 r1/t1 r0/t0 low f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68HC11EA9 54 mc68HC11EA9ts/d 9 analog-to-digital converter the analog-to-digital (a/d) converter system uses an all-capacitive charge-redistribution technique to convert analog signals to digital values. the mc68hc(7)11ea9 a/d converter system, a four-channel multiplexed-input successive-approximation converter, is accurate to 1 least significant bit (lsb). it does not require external sample and hold circuits because of the type of charge-redistribution tech- nique used. dedicated pins v rh and v rl provide the reference supply voltage inputs. a multiplexer allows the single a/d converter to select one of 16 analog signals. figure 14 a/d block diagram ea9 a/d block pe0 an0 pe1 an1 pe2 an2 pe3 an3 pe4 an4 pe5 an5 pe6 an6 pe7 an7 analog mux 8-bit capacitive dac with sample and hold successive approximation register and control adctl a/d control cb cc cd mult scan ccf ca adr1 a/d result 1 adr2 a/d result 2 adr3 a/d result 3 adr4 a/d result 4 result register interface result internal data bus v rh v rl f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC11EA9 motorola mc68HC11EA9ts/d 55 figure 15 a/d conversion sequence figure 16 electrical model of an a/d input pin (sample mode) msb 4 cycles e clock write to adctl bit 6 2 cyc bit 5 2 cyc bit 4 2 cyc bit 3 2 cyc bit 2 2 cyc bit 1 2 cyc lsb 2 cyc end 12 e cycles sample analog input successive approximation sequence 2 cyc convert fourth channel and update adr4 convert third channel and update adr3 convert second channel and update adr2 convert first channel and update adr1 set ccf flag repeat sequence if scan = 1 e cycles 128 96 64 32 0 ea9 a/d conversion tim ea9 analog input pin analog input pin 400 na junction leakage < 2 pf + ~20 v ?~0.7 v ~20 pf dac capacitance v rl diffusion and poly coupler < 4 k input protection device * this analog switch is closed only during the 12-cycle sample time. * f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola mc68HC11EA9 56 mc68HC11EA9ts/d ccf ?conversions complete flag set after an a/d conversion cycle is completed. ccf is cleared by a write to adctl. 0 = the a/d converter is currently performing a conversion sequence 1 = the a/d converter has completed a conversion, placed the result in the appropriate result reg- ister and is currently idle bit 6 ?not implemented always reads zero scan ?continuous scan control 0 = do four conversions and stop 1 = convert four channels in selected group continuously mult ?multiple channel/single channel control 0 = convert single channel selected 1 = convert four channels in selected group cd?a ?channel select d through a adctl a/d control/status $1030 bit 7 654321 bit 0 ccf scan mult cd cc cb ca reset: i 0 iiiiii table 23 a/d converter channel select control bits channel select control bits channel result in adrx if cd cc cb ca signal mult = 1 0000 an0 adr1 0001 an1 adr2 0010 an2 adr3 0011 an3 adr4 0100 an4 adr1 0101 an5 adr2 0110 an6 adr3 0111 an7 adr4 1000 reserved 1001 reserved 1010 reserved 1011 reserved 1100 v rh * adr1 1101 v rl * adr2 1110 (v rh )/2* adr3 1111 reserved adr4 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mc68HC11EA9 motorola mc68HC11EA9ts/d 57 adpu ?a/d converter power-up 0 = a/d converter disabled and powered down 1 = a/d converter is enabled and powered on csel ?clock select 0 = a/d and eeprom use the system e clock 1 = a/d and eeprom use internal rc clock irqe ?irq select edge-sensitive only refer to 5 resets and interrupts . dly ?enable oscillator start-up delay 0 = no stabilization delay on exit from stop mode. 1 = a delay of approximately 4000 e-clock cycles is imposed as the mcu exits stop mode. cme ?clock monitor enable refer to 5 resets and interrupts . bit 2 ?not implemented always reads zero cr[1:0] ?cop timer rate select refer to 5 resets and interrupts . adr1?dr4 a/d results $1031?1034 $1031 bit 7 654321 bit 0 adr1 $1032 bit 7 654321 bit 0 adr2 $1033 bit 7 654321 bit 0 adr3 $1034 bit 7 654321 bit 0 adr4 table 24 analog input to 8-bit result translation bit 7 654321 bit 0 % (1) 50% 25% 12.5% 6.25% 3.12% 1.56% 0.78% 0.39% volts (2) 2.5 1.250 0.625 0.3125 0.1562 0.0781 0.0391 0.0195 (1) % of v rh ?v rl (2) volts for v rl = 0; v rh = 5.0 v option system configuration options $1039 bit 7 654321 bit 0 adpu csel irqe* dly* cme cr1* cr0* reset: 00010000 * can be written only once in first 64 cycles after reset in normal modes, or at any time in special modes. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. ?ypical?parameters can and do vary in different applications. all operating parameters, including ?ypicals?must be validated for each customer application by customer? technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. literature distribution centers: usa: motorola literature distribution, p.o. box 20912, phoenix, arizona 85036. europe: motorola ltd., european literature centre, 88 tanners drive, blakelands, milton keynes, mk14 5bp, england. japan: nippon motorola ltd., 4-32-1, nishi-gotanda, shinagawa-ku, tokyo 141 japan. asia-pacific: motorola semiconductors h.k. ltd., silicon harbour centre, no. 2 dai king street, tai po industrial estate, tai po, n.t., hong kong. technical information : motorola inc. semiconductor products sector technical responsiveness center (800) 521-6274. document comments : fax (512) 891-2638. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . |
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